Patents by Inventor Yu Ying Lin
Yu Ying Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230157005Abstract: A semiconductor device includes a substrate, a bitline, a bitline contact and a land pad. The bitline is over the substrate. The bitline contact is in contact with a bottom of the bitline and in the substrate. The bitline contact includes a first portion and a second portion below the first portion, and the first portion is wider than the second portion from a cross-section view. A word line is adjacent to the bitline contact. A land pad is on the substrate, and the land pad is adjacent to the word line, such that the word line is between the bitline contact and the land pad.Type: ApplicationFiled: November 16, 2021Publication date: May 18, 2023Inventor: Yu-Ying LIN
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Patent number: 11641735Abstract: A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.Type: GrantFiled: October 18, 2021Date of Patent: May 2, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Yu-Ying Lin
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Publication number: 20230124715Abstract: A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.Type: ApplicationFiled: October 18, 2021Publication date: April 20, 2023Inventor: Yu-Ying Lin
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Patent number: 11243198Abstract: A gas sensing device is adapted to detect a concentration of a target gas. The gas sensing device comprises a dielectric layer, a reference sensing portion, a target sensing portion, and a controller. The dielectric layer is disposed on a surface. The reference sensing portion and the target sensing portion are respectively disposed on a supporting side of the dielectric layer, with said supporting side facing away from the surface. The reference sensing portion includes a first conductive layer and a first sensing layer with low sensitivity to the target gas. The target sensing portion includes a second conductive layer and a second sensing layer with high sensitivity to the target gas. The controller obtains the immittance values of the first conductive layer and the second conductive layer, and calculates a concentration value of the target gas according to the immittance values and a correlation function.Type: GrantFiled: May 20, 2020Date of Patent: February 8, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Ying Lin, Ying-Che Lo, Chung-Yi Hsu, Po-Jen Su
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Publication number: 20210190744Abstract: A gas sensing device is adapted to detect a concentration of a target gas. The gas sensing device comprises a dielectric layer, a reference sensing portion, a target sensing portion, and a controller. The dielectric layer is disposed on a surface. The reference sensing portion and the target sensing portion are respectively disposed on a supporting side of the dielectric layer, with said supporting side facing away from the surface. The reference sensing portion includes a first conductive layer and a first sensing layer with low sensitivity to the target gas. The target sensing portion includes a second conductive layer and a second sensing layer with high sensitivity to the target gas. The controller obtains the immittance values of the first conductive layer and the second conductive layer, and calculates a concentration value of the target gas according to the immittance values and a correlation function.Type: ApplicationFiled: May 20, 2020Publication date: June 24, 2021Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Ying LIN, Ying-Che LO, Chung-Yi HSU, Po-Jen SU
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Patent number: 10446667Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.Type: GrantFiled: May 7, 2019Date of Patent: October 15, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Yi-Liang Ye, Sung-Yuan Tsai, Chun-Wei Yu, Yu-Ren Wang, Zhen Wu, Tai-Yen Lin
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Publication number: 20190280106Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.Type: ApplicationFiled: May 7, 2019Publication date: September 12, 2019Inventors: Yu-Ying Lin, Yi-Liang Ye, Sung-Yuan Tsai, Chun-Wei Yu, Yu-Ren Wang, Zhen Wu, Tai-Yen Lin
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Patent number: 10381228Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.Type: GrantFiled: February 25, 2015Date of Patent: August 13, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Ted Ming-Lang Guo, Chin-Cheng Chien, Chih-Chien Liu, Hsin-Kuo Hsu, Chin-Fu Lin, Chun-Yuan Wu
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Patent number: 10366991Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.Type: GrantFiled: January 25, 2018Date of Patent: July 30, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsu Ting, Yu-Ying Lin, Yen-Hsing Chen, Chun-Jen Chen, Chun-Wei Yu, Keng-Jen Lin, Yu-Ren Wang
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Publication number: 20190221562Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.Type: ApplicationFiled: January 25, 2018Publication date: July 18, 2019Inventors: Hsu Ting, Yu-Ying Lin, Yen-Hsing Chen, Chun-Jen Chen, Chun-Wei Yu, Keng-Jen Lin, Yu-Ren Wang
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Patent number: 10332981Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.Type: GrantFiled: April 2, 2018Date of Patent: June 25, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Yi-Liang Ye, Sung-Yuan Tsai, Chun-Wei Yu, Yu-Ren Wang, Zhen Wu, Tai-Yen Lin
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Patent number: 10199485Abstract: A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. The first quantum wire includes the first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. And the second quantum wire includes the second semiconductor material.Type: GrantFiled: January 18, 2017Date of Patent: February 5, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 10128366Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.Type: GrantFiled: February 6, 2018Date of Patent: November 13, 2018Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
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Publication number: 20180204939Abstract: A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. The first quantum wire includes the first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. And the second quantum wire includes the second semiconductor material.Type: ApplicationFiled: January 18, 2017Publication date: July 19, 2018Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang
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Publication number: 20180158943Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.Type: ApplicationFiled: February 6, 2018Publication date: June 7, 2018Inventors: Yu-Ying Lin, Kuan Hsuan KU, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu LIN, Chun Yao YANG, Yu-Ren Wang, Neng-Hui Yang
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Patent number: 9966266Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.Type: GrantFiled: April 25, 2016Date of Patent: May 8, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Chun-Wei Yu, Kuang-Hsiu Chen, Yi-Liang Ye, Hsu Ting, Neng-Hui Yang
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Patent number: 9929264Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.Type: GrantFiled: June 20, 2017Date of Patent: March 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
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Publication number: 20170365703Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.Type: ApplicationFiled: June 20, 2017Publication date: December 21, 2017Inventors: Yu-Ying LIN, Kuan Hsuan KU, I-Cheng HU, Chueh-Yang LIU, Shui-Yen LU, Yu Shu LIN, Chun Yao YANG, Yu-Ren WANG, Neng-Hui YANG
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Publication number: 20170309485Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.Type: ApplicationFiled: April 25, 2016Publication date: October 26, 2017Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Chun-Wei Yu, Kuang-Hsiu Chen, Yi-Liang Ye, Hsu Ting, Neng-Hui Yang
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Patent number: 9782537Abstract: A portable infusion device adapted to hold an infusion bag is provided. The infusion bag includes a bag body and an infusion tube connected to the bag. The portable infusion device includes a case, a plate and an elevating mechanism. The case includes an accommodating space for accommodating the bag body. The case has an aperture. The infusion tube is adapted to pass through the aperture. The plate is disposed in the receiving space and is adapted to carry the bag body. The elevating mechanism is disposed in the accommodating space and is movably connected to the case. The plate is fixed on the elevating mechanism. The elevating mechanism is adapted to push the plate to move. The portable infusion device is easily carried in use.Type: GrantFiled: July 16, 2015Date of Patent: October 10, 2017Inventors: Sheng-Lian Lin, Yu-Ying Lin, Tung-Yi Lin