Patents by Inventor Yu Ying Lin

Yu Ying Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10366991
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: July 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsu Ting, Yu-Ying Lin, Yen-Hsing Chen, Chun-Jen Chen, Chun-Wei Yu, Keng-Jen Lin, Yu-Ren Wang
  • Publication number: 20190221562
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 18, 2019
    Inventors: Hsu Ting, Yu-Ying Lin, Yen-Hsing Chen, Chun-Jen Chen, Chun-Wei Yu, Keng-Jen Lin, Yu-Ren Wang
  • Patent number: 10332981
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Yi-Liang Ye, Sung-Yuan Tsai, Chun-Wei Yu, Yu-Ren Wang, Zhen Wu, Tai-Yen Lin
  • Patent number: 10199485
    Abstract: A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. The first quantum wire includes the first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. And the second quantum wire includes the second semiconductor material.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang
  • Patent number: 10128366
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: November 13, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
  • Publication number: 20180204939
    Abstract: A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. The first quantum wire includes the first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. And the second quantum wire includes the second semiconductor material.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 19, 2018
    Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang
  • Publication number: 20180158943
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.
    Type: Application
    Filed: February 6, 2018
    Publication date: June 7, 2018
    Inventors: Yu-Ying Lin, Kuan Hsuan KU, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu LIN, Chun Yao YANG, Yu-Ren Wang, Neng-Hui Yang
  • Patent number: 9966266
    Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Chun-Wei Yu, Kuang-Hsiu Chen, Yi-Liang Ye, Hsu Ting, Neng-Hui Yang
  • Patent number: 9929264
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: March 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
  • Publication number: 20170365703
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 21, 2017
    Inventors: Yu-Ying LIN, Kuan Hsuan KU, I-Cheng HU, Chueh-Yang LIU, Shui-Yen LU, Yu Shu LIN, Chun Yao YANG, Yu-Ren WANG, Neng-Hui YANG
  • Publication number: 20170309485
    Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.
    Type: Application
    Filed: April 25, 2016
    Publication date: October 26, 2017
    Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Chun-Wei Yu, Kuang-Hsiu Chen, Yi-Liang Ye, Hsu Ting, Neng-Hui Yang
  • Patent number: 9782537
    Abstract: A portable infusion device adapted to hold an infusion bag is provided. The infusion bag includes a bag body and an infusion tube connected to the bag. The portable infusion device includes a case, a plate and an elevating mechanism. The case includes an accommodating space for accommodating the bag body. The case has an aperture. The infusion tube is adapted to pass through the aperture. The plate is disposed in the receiving space and is adapted to carry the bag body. The elevating mechanism is disposed in the accommodating space and is movably connected to the case. The plate is fixed on the elevating mechanism. The elevating mechanism is adapted to push the plate to move. The portable infusion device is easily carried in use.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: October 10, 2017
    Inventors: Sheng-Lian Lin, Yu-Ying Lin, Tung-Yi Lin
  • Publication number: 20170243749
    Abstract: A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H2O2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.
    Type: Application
    Filed: February 22, 2016
    Publication date: August 24, 2017
    Inventors: Chueh-Yang Liu, Chun-Wei Yu, Yu-Ying Lin, Yu-Ren Wang
  • Patent number: 9741818
    Abstract: A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: August 22, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chueh-Yang Liu, Yu-Ying Lin, I-cheng Hu, Tien-I Wu, Yu-Shu Lin, Yu-Ren Wang
  • Patent number: 9741572
    Abstract: A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H2O2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: August 22, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chueh-Yang Liu, Chun-Wei Yu, Yu-Ying Lin, Yu-Ren Wang
  • Patent number: 9716165
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: July 25, 2017
    Assignee: United Microelectronics Corporation
    Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
  • Publication number: 20170170296
    Abstract: A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 15, 2017
    Inventors: Chueh-Yang Liu, Yu-Ying Lin, I-cheng Hu, Tien-I Wu, Yu-Shu Lin, Yu-Ren Wang
  • Patent number: 9633904
    Abstract: A method for manufacturing a semiconductor device with epitaxial structure includes following steps: A substrate including a plurality of gate structures formed thereon is provided, and a spacer is respectively formed on sidewalls of each gate structure. Next, a first etching process is performed to form a first recess respectively at two sides of the gate structures and followed by performing an ion implantation to the first recesses. After the ion implantation, a second etching process is performed to widen the first recesses to form widened first recesses and to form a second recess respectively at a bottom of each widened first recess. Then, an epitaxial structure is respectively formed in the widened first recesses and the second recesses.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: April 25, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Neng-Hui Yang
  • Patent number: 9530886
    Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, and a plurality of hyper-sigma (?) shaped epitaxial stressors. The substrate includes a first semiconductor material, and the hyper-? shaped epitaxial stressors include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The hyper-? shaped epitaxial stressors respectively include a first portion, a second portion and a neck physically connecting the first portion and the second portion. The first portion includes a pair of first tips pointing toward the gate structure in a cross-sectional view. The second portion includes a pair of second tips pointing toward the gate structure in the cross-sectional view. The neck includes a first slanted surface in the first portion and a second slanted surface in the second portion.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: December 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Neng-Hui Yang
  • Patent number: 9502244
    Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, next, a first dry etching process is performed, to form a recess in the substrate. Afterwards, an ion implantation process is performed to a bottom surface of the recess, a wet etching process is then performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively, and a second dry etching process is performed, to etch partial bottom surface of the recess, wherein after the second dry etching process is performed, a lower portion of the recess has a U-shaped cross section profile.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: November 22, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Kuang-Hsiu Chen, Ted Ming-Lang Guo, Yu-Ren Wang