Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.

Abstract: A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.

Abstract: Provided herein are tetravalent antibodies that specifically bind to human PSGL-1. Unlike bivalent antibodies, these tetravalent antibodies contain a dimer of two monomers, with each monomer comprising two light chain variable (VL) domains and two heavy chain variable (VH) domains. This format allows for cross-linker/FcR-expressing cell-independent tetravalent antibodies against PSGL-1 that show enhanced efficacy as compared to bivalent PSGL-1 antibodies. These tetravalent antibodies can be used in a variety of diagnostic and therapeutic methods, including without limitation treating T-cell mediated inflammatory diseases, transplantations, and transfusions.

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

Abstract: The present invention relates to a method of debugging a targeted area or the whole network-on-chip (NOC) (101), whereby said targeted area or the whole NOC is triggered to enter into a freeze state before capturing of the state of the targeted area or the whole NOC (101) and unloading of the debug information, before finally said targeted area or the whole NOC is triggered to enter into an unfreeze state to allow forward progress to resume, using existing buffer storage, thus allowing user to debug and identify the source of issue without requiring a significant amount of extra storage.

Abstract: An in-cell optical sensing display panel includes a pixel array, a plurality of first optical sensors and a plurality of second optical sensors. The pixel array is disposed in an active area of the in-cell optical sensing display panel, and the active area includes a first region and a second region which surrounds the first region. The sensor array is disposed in the first region of the active area and is configured to sense a fingerprint of a finger touching a surface of the in-cell optical sensing display panel. The second optical sensors are disposed in the second region of the active area and are configured to sense ambient light, and the second optical sensors are not to be used for fingerprint sensing.

Abstract: A semiconductor device includes a substrate, a bitline, a bitline contact and a land pad. The bitline is over the substrate. The bitline contact is in contact with a bottom of the bitline and in the substrate. The bitline contact includes a first portion and a second portion below the first portion, and the first portion is wider than the second portion from a cross-section view. A word line is adjacent to the bitline contact. A land pad is on the substrate, and the land pad is adjacent to the word line, such that the word line is between the bitline contact and the land pad.

Abstract: A semiconductor structure includes a semiconductor substrate; a spacer located in a trench of the semiconductor substrate, wherein the spacer includes two trench nitride layers and an empty gap sandwiched between the two trench nitride layers; a first nitride layer disposed to seal an exposed opening of the empty gap between the two trench nitride layers; a second nitride layer over the first nitride layer, wherein the second nitride layer has a higher density than the first nitride layer; and a third nitride layer having a first portion over the second nitride layer and a second portion disposed on sidewalls of the two trench nitride layers.

Abstract: The present invention relates generally to glycoconjugates comprising a saccharide covalently conjugated to a carrier protein through a spacer containing ((2-oxoethyl)thio)). In an aspect the invention provides oxo-eT linked glycoconjugates comprising a saccharide covalently conjugated to a carrier protein through a ((2-oxoethyl)thio) spacer having the formula (I): wherein: A is a group (C?X)m wherein X is S or O and m is 0 or 1; B is a bond, O, or CH2; and when m is 0, B can also be (C?O); R is a C2-C16 alkylene, C2-C16 heteroakylene, NH—C(?O)—C2-C16 alkylene, or NH—C(?O)—C2-C16 heteroakylene, wherein said alkylene and heteroalkylene are optionally substituted by 1, 2 or 3 groups independently selected from COOR? where R? is selected from H, methyl, ethyl or propyl. The invention further relates to immunogenic compositions comprising such glycoconjugates, and to methods for the preparation and use of such glycoconjugates and immunogenic compositions.

Abstract: A method of preparing polylactic acid (PLA) microsphere and polylactic-co-glycolic acid (PLGA) microsphere is provided, including the following steps. A first solution is provided, including polylactic acid or polylactic-co-glycolic acid and an organic solvent. A second solution is provided, including polyvinyl alcohol, sodium carboxymethyl cellulose and an aqueous solution. The first solution is added to the second solution and, at the same time, the second solution is agitated until polylactic acid is solidified to form a plurality of polylactic acid microspheres, or until polylactic-co-glycolic acid is solidified to form a plurality of polylactic-co-glycolic acid microspheres. The polylactic acid microspheres or polylactic-co-glycolic acid microspheres are collected.

Abstract: The present invention relates to new immunogenic compositions comprising conjugated Streptococcus pneumoniae capsular saccharide antigens (glycoconjugates) and uses thereof. Immunogenic compositions of the present invention will typically comprise at least one glycoconjugate from a S. pneumoniae serotype not found in PREVNAR®, SYNFLORIX® and/or PREVNAR 13®. The invention also relates to vaccination of human subjects, in particular infants and elderly, against pneumococcal infections using said novel immunogenic compositions.

Abstract: A dust-proof telecommunication system and a method for assembling a dust-proof mechanism are disclosed. The system includes a chassis including an opening on a top side thereof; a PCB located within the chassis; a memory module removably installed on the PCB; and a cover removably coupled to the top side of the chassis. The opening is positioned and shaped such that the memory module is accessible via the opening for easy replacement. The method includes inserting a strip into the opening such that a space is formed between a wall of the opening and the strip; and inserting the memory module into the space formed between the wall of the opening and the strip such that another strip located at a first side of the memory module contacts the wall and the strip contacts a second side of the memory module. The memory module is replaceably coupled to the PCB.

Abstract: An electronic package structure and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate, a conductive element, and a support structure. The substrate has a bottom surface and a lateral surface angled with the bottom surface. The conductive element is on the lateral surface of the substrate. The support structure is on the bottom surface of the substrate and configured to space the bottom surface from an external carrier. A lateral surface of the support structure is spaced apart from the lateral surface of the substrate by a first distance.

Abstract: Some embodiments of the invention provide a system for implementing multiple logical routers. The system includes a Kubernetes cluster that includes multiple nodes, with each node executing a set of pods. The set of pods include a first pod for performing a first set of data message processing operations for the multiple logical routers and at least one respective separate pod for each respective logical router of the multiple logical routers. Each respective pod is for performing a respective second set of data message processing operations for the respective logical router.

Abstract: A retractable handle assembly for an electronic device includes a base plate having a base plane, a sliding member, and a handle. The sliding member is movable along a first axis that is parallel to the base plane. The handle is movable along a second axis that is perpendicular to the base plane. The sliding member has a ramp surface and a wedge surface. The handle has a mating wedge surface. The ramp surface and the wedge surface are angularly oriented relative to the base plane. The ramp surface is angled to receive a first force, which is perpendicular relative to and directed towards the base plane. In response to the first force, the sliding member moves along the first axis and the wedge surface moves towards the mating wedge surface. The wedge surface moving towards the mating wedge surface causes a second force to deploy.

Abstract: A high-voltage device includes a substrate, a gate structure over the substrate, a drain region disposed on a first side of the gate structure, a plurality of source regions disposed on a second side of the gate structure, and a plurality of doped regions disposed on the second side of the gate structure. The gate structure includes a plurality of first portions and a plurality of second portions alternately arranged. Width of the first portions are greater than widths of the second portions. The source regions are adjacent to the first portions of the gate structures, and the doped regions are adjacent to the second portions of the gate structure. The drain region and the source regions include dopants of a first conductivity type, and the doped regions include dopants of a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Abstract: A memory controller system (and method of pre-scheduling memory transaction) for a storage device comprising a linked-list controller; a plurality of command buffers to store read commands or write commands, and an arbiter to issue command. Each command buffer containing variables set by the linked-list controller. The linked-list controller is configured to execute commands in sequence independent of logical command buffer sequence. The command buffer is configured to support read commands with maximum number of write commands. The linked-list controller is configured to merge multiple write commands that are going to the same address and snarfs read commands from write commands if both commands are going to the same address and the read commands that are snarfed are loaded into a separate command buffer. The variables contained in each of the command buffer indicates status and dependency of the command buffer to create a link forming a command sequence.

Abstract: The invention provides eTEC linked glycoconjugates comprising a saccharide covalently conjugated to a carrier protein through a (2-((2-oxoethyl)thio)ethyl)carbamate (eTEC) spacer, immunogenic compositions comprising such glycoconjugates, and methods for the preparation and use of such glycoconjugates and immunogenic compositions.

Abstract: A ruler device module is disclosed that includes top and bottom plates that are parallel, with the bottom plate defining a tray where the bottom plate extends beyond the top plate. The module further includes a pair of side plates on opposite sides of, and extending between, the top and bottom plate, with each side plate including a slot. Partitions are perpendicular to and between the top and bottom plates forming bays between adjacent partitions and the top and bottom plates. A handle structure is between the top and bottom plates and includes a handle configured to rotate between a recessed position and a use position. A nut structure is between the top plate and the bottom plate. The nut structure includes an aperture configured to engage a fastener of a chassis to secure the ruler device module to the chassis.

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.