Abstract: An integrated air valve structure includes a main body and two air valves. The main body is formed with two air passages not communicated with each other, a plurality of through holes disposed corresponding to the two air passages, and two valve mounting seats. One valve mounting seat is disposed corresponding to one of the through holes, the other valve mounting seat is disposed corresponding to two of the through holes belonging to the two air passages. The two air valves are disposed on the two valve mounting seats, each air valves includes an air plug facing at least one of the through holes, a valve body assembled with one of the two valve mounting seats for the air plug to move therein, and a coil disposed on the valve body for generating magnetic force to change a position of the air plug.

Abstract: An in-memory computing (IMC) memory device comprises a plurality of computing memory cells and a plurality of balance computing memory cells forming a plurality of memory strings. In programming, a first resistance state number of the balance computing memory cells is determined based on a first resistance state number of the computing memory cells of the memory string. In IMC operations, when a read voltage is applied to the computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents; the memory string currents charge a loading capacitor; a capacitor voltage of the loading capacitor is measured; and based a relationship between the capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.

Abstract: A voltage provision circuit includes a first NMOS transistor gated with a first control signal and sourced with a ground voltage, a second NMOS transistor gated with a second control signal complementary to the first control signal and sourced with the ground voltage, a first PMOS transistor sourced with a first supply voltage, a second PMOS transistor sourced with the first supply voltage, and a voltage modulation circuit that is coupled between the first to second PMOS transistors and the first to second NMOS transistors, and is configured to provide a first intermediate signal based on the first and second control signals. The first intermediate signal has a first logic state corresponding to the first supply voltage and a second logic state corresponding to a second supply voltage that is a fraction of the first supply voltage.

Abstract: An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.

Abstract: The disclosure relates to magnetic resonance imaging triggered by a prospective acquisition correction sequence. The technique comprises determining repetition time and an acquisition window time of a single-shot fast spin echo sequence; determining the maximum imaging layer number N in each physiological movement cycle on the basis of the acquisition window time and the repetition time, where N is a positive integer greater than or equal to 2; and enabling the single-shot fast spin echo sequence to obtain M layers of imaging data within at least one acquisition window time when the prospective acquisition correction sequence generates a trigger signal, where M is a positive integer greater than or equal to 2 and less than or equal to N. According to the present disclosure, a plurality of layers of imaging data are obtained within a single acquisition window time, thereby increasing a scanning speed and shortening imaging time.

Abstract: A reservoir device, comprises a first transistor and a second transistor. A gate of the first transistor is coupled to a write word line, a drain of the first transistor is coupled to a write bit line. A source of the second transistor is coupled to a read source line, a drain of the second transistor is coupled to a read bit line, and a gate of the second transistor is coupled to a source of the first transistor. A storage node is located on a coupling point between the gate of the second transistor and the source of the first transistor. The reservoir device selectively performs a write operation, a read operation or a refresh operation in response to an input voltage received by the write word line, the write bit line, the read source line and the read bit line respectively.

Abstract: The invention provides a detection air faucet, including a working chamber and a source port in communication with the working chamber. The working chamber is provided with a pressure sensing member for sensing a change in the pressure in the chamber, and the pressure in the working chamber is affected by an object connected to the source port. The pressure sensing member is provided with a working pressure range. Furthermore, the detection air faucet includes a working pressure maintaining mechanism implemented by a pressure release structure and a pressure maintaining structure. When the pressure in the working chamber exceeding the working pressure range, the working chamber discharges air by the pressure release structure, and when the pressure in the working chamber is lower than a pressure outside the detection air faucet, the air outside the detection air faucet entering into the working chamber by the pressure maintaining structure.

Abstract: According to one embodiment, an information processing device includes a processing circuit as a hardware processor and configured to establish encrypted tunnel communication with a second node by using a second encryption key subjected to encrypted relay transmission to the second node by a first encryption key shared, by quantum key distribution, with a plurality of first nodes adjacent to each other. The second node is one of the plurality of first nodes. The processing circuit is configured to cause a network interface (IF) unit to transfer a third encryption key to the second node by the encrypted tunnel communication.

Abstract: A memory device includes a first memory cell performing a logic operation. The first memory cell includes first and second switches. The first switch writes a first weight bit into a first storage node. The second switch generates a first current signal according to the first weight bit and a first input bit. The second switch receives a first bit line signal carrying the first input bit and a first word line signal. A control terminal of the second switch is coupled to the first storage node. When the first input bit has a first logic value, the first bit line signal and the first word line signal has a first voltage level. When the first input bit has a second logic value, the first bit line signal has a second voltage level smaller than the first voltage level.

Abstract: A light sensing method having a sensing order adjusting mechanism is provided. The method includes steps of: in a previous sensing cycle, sensing a first light signal that is emitted by both of an ambient light source and a light-emitting component and then is reflected by a tested object; in the previous sensing cycle, sensing a second light signal that is emitted by both of the ambient light source and the light-emitting component and then is reflected by the tested object; in the previous sensing cycle, sensing an ambient light signal emitted by only the ambient light source; and in a next sensing cycle, sensing the first light signal, the second light signal and the ambient light signal in an order different from that in the previous sensing cycle.

Abstract: A gas sensor includes a first electrode, a gas detecting layer disposed on the first electrode, and an electric-conduction enhanced electrode unit being electrically connected to the first electrode and the gas detecting layer. The electric-conduction enhanced electrode unit includes an electric-conduction enhancing layer and a second electrode electrically connected to the electric-conduction enhancing layer. The electric-conduction enhancing layer is electrically connected to the gas detecting layer and is made of an electrically conductive organic material.

Abstract: A universal memory device includes an array of universal memory cells. Each universal memory cell includes a write transistor and a read transistor. The write transistor has a gate terminal configured to receive a gate voltage to turn on or off the write transistor, a first terminal configured to receive a write voltage, and a second terminal coupled to a gate terminal of the read transistor. The read transistor includes a charge trap layer at the gate terminal of the read transistor. The charge trap layer is configured to: be unalterable when the first write voltage is applied at the first terminal of the write transistor, and be alterable when the second write voltage is applied at the first terminal of the write transistor to change a threshold voltage of the read transistor. The second write voltage is greater than the first write voltage.

Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a plurality of semiconductor layers vertically stacked, a plurality of inner spacers, each being disposed between two adjacent semiconductor layers. The structure also includes a source/drain feature in contact with each of the inner spacers, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and a cap layer disposed between the source/drain feature and each of the plurality of the semiconductor layers.

Abstract: A computer processing system is provided for enhancing video-based language learning. The system includes a video server for storing videos that use one or more languages to be learned. The system further includes a video metadata database for storing translations of sentences uttered in the videos, character profiles of characters appearing in the videos, and mappings between the sentences and a learner profile. The system also includes a learner profile database for storing learner profiles. The system additionally includes a semantic analyzer and matching engine for finding, for at least a given video and a given learner, alternative sentences for and responsive to the translations of the sentences uttered in the given video that conflict with a respective learner profile for the given learner. The computer processing system further includes a presentation system for playing back the given video and providing the alternative sentences to the given learner.

Abstract: The present invention provides a metal-nanoparticle-free surface-enhanced Raman scattering substrate, which comprises: an anodic aluminum oxide substrate with three-dimensional cavities, and a metal nano-film on the anodic aluminum oxide substrate. The surface-enhanced Raman scattering substrate of the present invention does not need to use metal nanoparticles, but instead uses a structure of metal nanofilm to generate a surface plasmonic resonance. Therefore, compared with the traditional surface-enhanced Raman scattering substrate with an addition of metal nanoparticles, the surface-enhanced Raman scattering substrate of the present invention has better uniformity, stability and reproducibility. The present invention utilizes an anodic aluminum oxide substrate with three-dimensional cavities, so that the surface-enhanced Raman scattering substrate has high sensitivity, high stability, and high reproducibility.

Abstract: The present invention provides a food detection system including: an extraction equipment, a liquid to be identified, a laser light source, a Raman spectrometer, and a metal-nanoparticle-free surface-enhanced Raman scattering substrate. Without an addition of metal nanoparticles, the surface-enhanced Raman scattering substrate of the present invention has better stability and reproducibility compared to those traditional surface-enhanced Raman scattering substrate with metal nano particles. The present invention utilizes an anodic aluminum oxide substrate with two-dimensional and three-dimensional cavities, so that the surface-enhanced Raman scattering substrate has high sensitivity, high stability, and high reproducibility, and may therefore shorten the detection time and production cost of food detection. The invention also provides a food detection method using the food detection system, which is cheap, fast, stable and reliable.

Abstract: A key management device according to an embodiment is a key management device managing an application key for encrypting a communication in an application network including a plurality of applications. The key management device includes a hardware processor configured to function as a collection unit, a calculation unit, a determination unit, and a communication unit. The collection unit collects, using quantum key distribution (QKD), resource information indicating a resource of a link for which a link key is generated. The calculation unit calculates metric for a key relay route including the link on the basis of the resource information. The determination unit determines a key relay route from among a plurality of key relay routes on the basis of the metric. The communication unit uses the key relay route determined by the determination unit to send, to a destination, an application key encrypted with the link key.

Abstract: Embodiments of the present disclosure provide a method for selectively forming a seed layer over semiconductor fins. Some embodiments provide forming the selective seed layer using a mono-silane at an increased temperature. Some embodiments provide depositing a hetero-crystalline silicon cap layer over the bottom-up gap layer to improve gap filling and tune profiles of fin structures.

Abstract: The present invention provides a training system and method, a testing system and method, a data filtering system and method, and a computer readable recording medium with stored program that includes verifying whether an object detection model has completed a training set learning and determining whether the object detection model is overfitting with a validation set, and outputting the training model as a master model before the object detection model is overfitting, and how to iterate the master model to match the test set test results and continuously maintain an online test level. The present invention provides a standardized method for achieving data marking consistency and training data selection.

Abstract: An optical driving mechanism is provided, including a movable portion, a fixed portion, a driving component and a first stopper component. The movable portion is configured to connect an optical element. The movable portion is movable relative to the fixed portion. The driving component is configured to drive the movable portion to move relative to the fixed portion. The first stopper component is configured to limit the range of movement of the movable portion relative to the fixed portion.