Patents by Inventor Yu-Yun Peng

Yu-Yun Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220139773
    Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.
    Type: Application
    Filed: January 13, 2022
    Publication date: May 5, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li WANG, Shuen-Shin LIANG, Yu-Yun PENG, Fang-Wei LEE, Chia-Hung CHU, Mrunal Abhijith KHADERBAD, Keng-Chu LIN
  • Publication number: 20220123152
    Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.
    Type: Application
    Filed: October 21, 2020
    Publication date: April 21, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Khaderbad Mrunal Abhijith, Keng-Chu LIN, Yu-Yun PENG
  • Publication number: 20220108919
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 7, 2022
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Patent number: 11282712
    Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile film having a second tensile stress that is less than the first tensile stress or a compressive film. The first insulating film and second insulating film are formed of a same material. A metal hard mask layer is formed on the second insulating film.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Yu-Yun Peng
  • Patent number: 11257753
    Abstract: The present disclosure provides an interconnect structure, including a substrate having a conductive region adjacent to a gate region, a contact over the conductive region, a first interlayer dielectric layer (ILD) surrounding the contact, a via over the contact, a first densified dielectric layer surrounding the via, wherein the densified dielectric layer has a first density, and a second ILD layer over the first ILD layer and surrounding the via, wherein the second ILD layer has a second density, the first density is greater than a second density.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Khaderbad Mrunal Abhijith, Yu-Yun Peng, Fu-Ting Yen, Chen-Han Wang, Tsu-Hsiu Perng, Keng-Chu Lin
  • Patent number: 11227794
    Abstract: A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Shuen-Shin Liang, Yu-Yun Peng, Fang-Wei Lee, Chia-Hung Chu, Mrunal Abhijith Khaderbad, Keng-Chu Lin
  • Patent number: 11158539
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature; etching a hole through the dielectric layer and exposing the conductive feature; depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature; depositing a second metal over the first metal; and annealing the structure including the first and the second metals.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Publication number: 20210280710
    Abstract: A device includes a semiconductive substrate, a fin structure, and an isolation material. The fin structure extends from the semiconductive substrate. The isolation material is over the semiconductive substrate and adjacent to the fin structure, wherein the isolation material includes a first metal element, a second metal element, and oxide.
    Type: Application
    Filed: May 23, 2021
    Publication date: September 9, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun PENG, Keng-Chu LIN
  • Publication number: 20210249318
    Abstract: A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material. The material may be formed using a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. The material may then be cured to remove a porogen and help to collapse channels within the material. As such, the material may be formed with a scaling factor of less than or equal to about 1.8.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 12, 2021
    Inventors: Yin-Jie Pan, Yu-Yun Peng
  • Publication number: 20210225692
    Abstract: Generally, examples are provided relating to filling gaps with a dielectric material, such as filling trenches between fins for Shallow Trench Isolations (STIs). In an embodiment, a first dielectric material is conformally deposited in a trench using an atomic layer deposition (ALD) process. After conformally depositing the first dielectric material, the first dielectric material is converted to a second dielectric material. In further examples, the first dielectric material can be conformally deposited in another trench, and a fill dielectric material can be flowed into the other trench and converted.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventor: Yu-Yun Peng
  • Publication number: 20210225762
    Abstract: The present disclosure provides an interconnect structure, including a substrate having a conductive region adjacent to a gate region, a contact over the conductive region, a first interlayer dielectric layer (ILD) surrounding the contact, a via over the contact, a first densified dielectric layer surrounding the via, wherein the densified dielectric layer has a first density, and a second ILD layer over the first ILD layer and surrounding the via, wherein the second ILD layer has a second density, the first density is greater than a second density.
    Type: Application
    Filed: May 27, 2020
    Publication date: July 22, 2021
    Inventors: KHADERBAD MRUNAL ABHIJITH, YU-YUN PENG, FU-TING YEN, CHEN-HAN WANG, TSU-HSIU PERNG, KENG-CHU LIN
  • Publication number: 20210202254
    Abstract: A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.
    Type: Application
    Filed: March 12, 2021
    Publication date: July 1, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun PENG, Chung-Chi KO, Keng-Chu LIN
  • Publication number: 20210202735
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Yu-Yun Peng, Fu-Ting Yen, Ting-Ting Chen, Keng-Chu Lin, Tsu-Hsiu Perng
  • Publication number: 20210193511
    Abstract: A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li WANG, Shuen-Shin LIANG, Yu-Yun PENG, Fang-Wei LEE, Chia-Hung CHU, Mrunal Abhijith KHADERBAD, Keng-Chu LIN
  • Patent number: 11018258
    Abstract: A device includes a semiconductor fin and a shallow trench isolation (STI) structure. The semiconductor fin extends from a semiconductor substrate. The STI structure is around a lower portion of the semiconductor fin, and the STI structure includes a liner layer and an isolation material. The liner layer includes a metal-contained ternary dielectric material. The isolation material is over the liner layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 10991636
    Abstract: A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material. The material may be formed using a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. The material may then be cured to remove a porogen and help to collapse channels within the material. As such, the material may be formed with a scaling factor of less than or equal to about 1.8.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Jie Pan, Yu-Yun Peng
  • Publication number: 20210118677
    Abstract: A s semiconductor device structure is provided. The structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The structure also includes a spacer element extending along a sidewall of the gate stack. The spacer element has a first portion, a second portion, a third portion, and a fourth portion. Each of the first portion, the second portion, the third portion, and the fourth portion conformally extends along the sidewall of the gate stack. The second portion is sandwiched between the first portion and the third portion, and the third portion is sandwiched between the second portion and the fourth portion. Each of the first portion and the third portion has a first atomic concentration of carbon, and each of the second portion and the fourth portion has a second atomic concentration of carbon. The second atomic concentration of carbon is different than the first atomic concentration of carbon.
    Type: Application
    Filed: December 10, 2020
    Publication date: April 22, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guan-Yao TU, Yu-Yun PENG
  • Patent number: 10971391
    Abstract: Generally, examples are provided relating to filling gaps with a dielectric material, such as filling trenches between fins for Shallow Trench Isolations (STIs). In an embodiment, a first dielectric material is conformally deposited in a trench using an atomic layer deposition (ALD) process. After conformally depositing the first dielectric material, the first dielectric material is converted to a second dielectric material. In further examples, the first dielectric material can be conformally deposited in another trench, and a fill dielectric material can be flowed into the other trench and converted.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Yun Peng
  • Publication number: 20210098295
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature; etching a hole through the dielectric layer and exposing the conductive feature; depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature; depositing a second metal over the first metal; and annealing the structure including the first and the second metals.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Patent number: 10957543
    Abstract: A method includes forming an interlayer dielectric (ILD) and a gate structure over a substrate. The gate structure is surrounded by the ILD. The gate structure is etched to form a recess. A first dielectric layer is deposited over sidewalls and a bottom of the recess and over a top surface of the ILD using a first Si-containing precursor. A second dielectric layer is deposited over and in contact with the first dielectric layer using a second Si-containing precursor different from the first Si-containing precursor. A third dielectric layer is deposited over and in contact with the second dielectric layer using the first Si-containing precursor. Portions of the first, second, and third dielectric layer over the top surface of the ILD are removed.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Chung-Chi Ko, Keng-Chu Lin