Patents by Inventor Yu-Yun Peng

Yu-Yun Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12255249
    Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Keng-Chu Lin, Yu-Yun Peng
  • Patent number: 12255239
    Abstract: The present disclosure describes a semiconductor device that includes a transistor. The transistor includes a source/drain region that includes a front surface and a back surface opposite to the front surface. The transistor includes a salicide region on the back surface and a channel region in contact with the source/drain region. The channel region has a front surface co-planar with the front surface of the source/drain region. The transistor further includes a gate structure disposed on a front surface of the channel region. The semiconductor device also includes a backside contact structure that includes a conductive contact in contact with the salicide region and a liner layer surrounding the conductive contact.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Keng-Chu Lin, Yu-Yun Peng
  • Publication number: 20250081492
    Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The method includes removing a first semiconductor layer disposed between a second semiconductor layer and a third semiconductor layer and performing an oxide refill process to form a seamless dielectric material between the second and third semiconductor layers. The oxide refill process includes exposing the second and third semiconductor layers to a silicon-containing precursor at a first flow rate for a first duration to form a monolayer, and exposing the monolayer to an oxygen-containing precursor at a second flow rate for a second duration to form the seamless dielectric material, the second flow rate is about twice to about 20 times the first flow rate, and the second duration is about twice to about 20 times the first duration.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 6, 2025
    Inventors: Kuei-Lin CHAN, Wei-Ting YEH, Fu-Ting YEN, Yu-Yun PENG, Keng-Chu LIN
  • Patent number: 12211815
    Abstract: A micro LED display panel is provided. The micro LED display panel includes a driving substrate and a plurality of bonding pads disposed on the driving substrate and spaced apart from each other. The micro LED display panel also includes a plurality of micro LED structures electrically connected to the bonding pads. Each micro LED structure includes at least one electrode disposed on the side of the micro LED structure facing the driving substrate. The electrode has a normal contact surface and a side contact surface. The normal contact surface faces the driving substrate, and the side contact surface is laterally connected to the corresponding bonding pad.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: January 28, 2025
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Shiang-Ning Yang, Yung-Chi Chu, Yu-Yun Lo, Bo-Wei Wu, Yu-Ya Peng
  • Publication number: 20250014943
    Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 9, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zheng Yong LIANG, Wei-Ting YEH, I-Han HUANG, Chen-Hao WU, An-Hsuan LEE, Huang-Lin CHAO, Yu-Yun PENG, Keng-Chu LIN
  • Publication number: 20250006687
    Abstract: An integrated circuit die with two material layers having metal nano-particles and the method of forming the same are provided. The integrated circuit die includes a device layer comprising a first transistor, a first interconnect structure on a first side of the device layer, a first material layer on the first interconnect structure, wherein the first material layer comprises first metal nano-particles, and a second material layer bonded to the first material layer, wherein the second material layer comprises second metal nano-particles, and wherein the first material layer and the second material layer share an interface.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Zheng-Yong Liang, Wei-Ting Yeh, Han-De Chen, Chen-Fong Tsai, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240387653
    Abstract: The present disclosure describes a semiconductor device that includes a transistor. The transistor includes a source/drain region that includes a front surface and a back surface opposite to the front surface. The transistor includes a salicide region on the back surface and a channel region in contact with the source/drain region. The channel region has a front surface co-planar with the front surface of the source/drain region. The transistor further includes a gate structure disposed on a front surface of the channel region. The semiconductor device also includes a backside contact structure that includes a conductive contact in contact with the salicide region and a liner layer surrounding the conductive contact.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mrunal Abhijith KHADERBAD, Keng-Chu Lin, Yu-Yun Peng
  • Publication number: 20240387358
    Abstract: A method for forming an interconnect structure is provided. The method includes the following operations. A contact is formed over a substrate. An interlayer dielectric (ILD) layer is formed over the contact and the substrate. An opening is formed in the ILD layer thereby exposing a portion of the contact. A densified dielectric layer is formed at an exposed surface of the ILD layer by the opening and an oxide layer over the portion of the contact by irradiating a microwave on the exposed surface of the ILD layer.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: KHADERBAD MRUNAL ABHIJITH, YU-YUN PENG, FU-TING YEN, CHEN-HAN WANG, TSU-HSIU PERNG, KENG-CHU LIN
  • Publication number: 20240363744
    Abstract: A semiconductor device includes a substrate, a first active structure, a second active structure, a wall and a STI layer. The first active structure is formed on the substrate. The second active structure is formed on the substrate. The wall is formed between the first active structure and the second active structure. The STI layer is formed adjacent to the first active structure and has an upper surface. A distance between a spacer of the first active structure and the upper surface of the STI layer may range between 0 and 50 nanometers.
    Type: Application
    Filed: April 25, 2023
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Ting YEN, Yu-Yun PENG, Kuei-Lin CHAN
  • Publication number: 20240355733
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first nitride-containing layer on a side of a carrier substrate, first semiconductor devices thermally coupled to the first nitride-containing layer, a first interconnect structure physically and electrically coupled to first sides of the first semiconductor devices, and a first metal-containing dielectric layer bonding the first nitride-containing layer to the first interconnect structure. A thermal conductivity of the first nitride-containing layer is greater than a thermal conductivity of the first metal-containing dielectric layer.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Yong Liang, Wei-Ting Yeh, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240355805
    Abstract: Provided is a method of forming a semiconductor structure including: bonding a device wafer onto a carrier wafer; forming a support structure between an edge of the device wafer and an edge of the carrier wafer, wherein the support structure surrounds a device layer of the device wafer along a closed path; removing a substrate and a portion of a bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structures while the support structure is in place; and removing the support structure through an acid etchant.
    Type: Application
    Filed: April 21, 2023
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ting Yeh, Zheng-Yong Liang, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240347342
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Publication number: 20240332419
    Abstract: A device includes a semiconductive substrate, a fin structure, and an isolation material. The fin structure extends from the semiconductive substrate. The isolation material is over the semiconductive substrate and adjacent to the fin structure, wherein the isolation material includes a first metal element, a second metal element, and oxide.
    Type: Application
    Filed: June 6, 2024
    Publication date: October 3, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun PENG, Keng-Chu LIN
  • Publication number: 20240282761
    Abstract: A carrier structure and methods of forming and using the same are described. In some embodiments, the method includes forming one or more devices over a substrate, forming a first interconnect structure over the one or more devices, and bonding the first interconnect structure to a carrier structure. The carrier structure includes a semiconductor substrate, a release layer, and a first dielectric layer, and the release layer includes a metal nitride. The method further includes flipping over the one or more devices so the carrier structure is located at a bottom, performing backside processes, flipping over the one or more devices so the carrier structure is located at a top, and exposing the carrier structure to IR lights. Portions of the release layer are separated from the first dielectric layer.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Inventors: Zheng Yong Liang, Wei-Ting Yeh, Jyh-Cherng Sheu, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240274539
    Abstract: An interconnect structure, along with methods of forming such, are described. In some embodiments, the structure includes a first dielectric layer disposed over one or more devices, a first conductive feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first conductive feature, and a second conductive feature disposed in the second dielectric layer. The second conductive feature is electrically connected to the first conductive feature. The structure further includes a heat dissipation layer disposed between the first and second dielectric layers, and the heat dissipation layer partially surrounds the second conductive feature and is electrically isolated from the first and second conductive features.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 15, 2024
    Inventors: Yu-Yun PENG, Keng-Chu LIN
  • Patent number: 12051592
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Publication number: 20240249947
    Abstract: A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.
    Type: Application
    Filed: February 6, 2024
    Publication date: July 25, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun PENG, Chung-Chi KO, Keng-Chu LIN
  • Publication number: 20240243009
    Abstract: A device includes source/drain regions, a gate structure, a source/drain contact, and a tungsten structure. The source/drain regions are over a substrate. The gate structure is between the source/drain regions. The source/drain contact is over one of the source/drain regions. The tungsten structure is over the source/drain contact. The tungsten structure includes a lower portion and an upper portion above the lower portion. The upper portion has opposite sidewalls respectively set back from opposite sidewalls of the lower portion of the tungsten structure.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li WANG, Shuen-Shin LIANG, Yu-Yun PENG, Fang-Wei LEE, Chia-Hung CHU, Mrunal Abhijith KHADERBAD, Keng-Chu LIN
  • Patent number: 12034075
    Abstract: A device includes a semiconductive substrate, a fin structure, and an isolation material. The fin structure extends from the semiconductive substrate. The isolation material is over the semiconductive substrate and adjacent to the fin structure, wherein the isolation material includes a first metal element, a second metal element, and oxide.
    Type: Grant
    Filed: May 23, 2021
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 11996363
    Abstract: An interconnect structure, along with methods of forming such, are described. In some embodiments, the structure includes a first dielectric layer disposed over one or more devices, a first conductive feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first conductive feature, and a second conductive feature disposed in the second dielectric layer. The second conductive feature is electrically connected to the first conductive feature. The structure further includes a heat dissipation layer disposed between the first and second dielectric layers, and the heat dissipation layer partially surrounds the second conductive feature and is electrically isolated from the first and second conductive features.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Yun Peng, Keng-Chu Lin