Patents by Inventor Yu-Yun Peng
Yu-Yun Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190157075Abstract: A structure and a formation method of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate. The method also includes forming a sealing layer over a sidewall of the gate stack using an atomic layer deposition process. The atomic layer deposition process includes alternately and sequentially introducing a first silicon-containing precursor gas and a second silicon-containing precursor gas over the sidewall of the gate stack to form the sealing layer. The second silicon-containing precursor gas has a different atomic concentration of carbon than that of the first silicon-containing precursor gas. The method further includes partially removing the sealing layer to form a sealing element over the sidewall of the gate stack.Type: ApplicationFiled: October 11, 2018Publication date: May 23, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Guan-Yao TU, Yu-Yun PENG
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Patent number: 10290739Abstract: A method includes etching a semiconductor substrate to form a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate. A first liner layer is formed on sidewalls and a bottom of the trench. The trench is filled with a dielectric material after depositing the first liner layer. The dielectric material and the first liner layer include substantially the same metal-contained ternary dielectric material. Excess portions of the dielectric material and the first liner layer over the top surface of the semiconductor substrate are removed.Type: GrantFiled: August 2, 2018Date of Patent: May 14, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Yun Peng, Keng-Chu Lin
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Publication number: 20190139757Abstract: Methods of forming a silicon oxide layer and a semiconductor structure are disclosed. The method of forming the silicon oxide layer includes the following steps. A silicon-containing precursor, an oxygen-containing precursor and an oxygen radical are provided to form a silicon oxide layer containing water. A thermal process is performed on the silicon oxide layer to diffuse the water into the silicon oxide layer and oxidize the silicon oxide layer by using the water as oxidizer.Type: ApplicationFiled: June 29, 2018Publication date: May 9, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yu-Yun Peng
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Publication number: 20190103276Abstract: A method includes forming an interlayer dielectric (ILD) and a gate structure over a substrate. The gate structure is surrounded by the ILD. The gate structure is etched to form a recess. A first dielectric layer is deposited over sidewalls and a bottom of the recess and over a top surface of the ILD using a first Si-containing precursor. A second dielectric layer is deposited over and in contact with the first dielectric layer using a second Si-containing precursor different from the first Si-containing precursor. A third dielectric layer is deposited over and in contact with the second dielectric layer using the first Si-containing precursor. Portions of the first, second, and third dielectric layer over the top surface of the ILD are removed.Type: ApplicationFiled: June 22, 2018Publication date: April 4, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Yun PENG, Chung-Chi KO, Keng-Chu LIN
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Publication number: 20190103485Abstract: A method includes etching a semiconductor substrate to form a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate. A first liner layer is formed on sidewalls and a bottom of the trench. The trench is filled with a dielectric material after depositing the first liner layer. The dielectric material and the first liner layer include substantially the same metal-contained ternary dielectric material. Excess portions of the dielectric material and the first liner layer over the top surface of the semiconductor substrate are removed.Type: ApplicationFiled: August 2, 2018Publication date: April 4, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Yun PENG, Keng-Chu LIN
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Publication number: 20190096752Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: ApplicationFiled: November 26, 2018Publication date: March 28, 2019Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
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Publication number: 20190035704Abstract: A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material. The material may be formed using a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. The material may then be cured to remove a porogen and help to collapse channels within the material. As such, the material may be formed with a scaling factor of less than or equal to about 1.8.Type: ApplicationFiled: January 15, 2018Publication date: January 31, 2019Inventors: Yin-Jie Pan, Yu-Yun Peng
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Patent number: 10141220Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: GrantFiled: September 1, 2017Date of Patent: November 27, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
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Patent number: 10134632Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.Type: GrantFiled: February 6, 2017Date of Patent: November 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Joung-Wei Liou, Hui-Chun Yang, Yu-Yun Peng, Keng-Chu Lin
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Patent number: 9941214Abstract: Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.Type: GrantFiled: August 15, 2013Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Kuang-Yuan Hsu
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Publication number: 20170365508Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: ApplicationFiled: September 1, 2017Publication date: December 21, 2017Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
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Publication number: 20170365561Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile film having a second tensile stress that is less than the first tensile stress or a compressive film. The first insulating film and second insulating film are formed of a same material. A metal hard mask layer is formed on the second insulating film.Type: ApplicationFiled: June 20, 2016Publication date: December 21, 2017Inventors: Jung-Hau SHIU, Chung-Chi KO, Tze-Liang LEE, Yu-Yun PENG
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Patent number: 9818638Abstract: A method of forming a semiconductor device includes forming a low-k dielectric layer over a substrate and forming a first dielectric layer on the low-k dielectric layer. A first metal hard mask layer is formed on the first dielectric layer, and a second dielectric layer is formed on the first metal hard mask layer. A second metal hard mask layer is formed on the second dielectric layer, and a first trench opening is formed in the second metal hard mask layer and the second dielectric layer exposing the first metal hard mask layer. A first via opening is formed in the exposed first metal hard mask layer in the first trench opening, and the first trench opening and first via opening are extended into the low-k dielectric layer to form a first trench and a first via.Type: GrantFiled: April 18, 2017Date of Patent: November 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Yun Peng, Chung-Chi Ko, Shing-Chyang Pan
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Patent number: 9754818Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: GrantFiled: August 2, 2016Date of Patent: September 5, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
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Patent number: 9748134Abstract: A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion layer over the first adhesion layer, where the second adhesion layer is formed using an inert gas with a first flow rate under a first RF power. Additionally, the method includes forming a low-k dielectric layer over the second adhesion layer, where the low-k dielectric layer is formed using the inert gas with a second flow rate under a second RF power under at least one of the following two conditions: 1) the second flow rate is different from the first flow rate; or 2) the second RF power is different from the first RF power. Furthermore, the method includes forming an opening in the dielectric layer, the second adhesion layer, and the first adhesion layer. Additionally, the method includes forming a conductor in the opening.Type: GrantFiled: February 8, 2016Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Cheng Shih, Yu-Yun Peng, Chia Cheng Chou, Joung-Wei Liou
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Publication number: 20170200636Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: ApplicationFiled: August 2, 2016Publication date: July 13, 2017Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
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Publication number: 20170148676Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.Type: ApplicationFiled: February 6, 2017Publication date: May 25, 2017Inventors: Joung-Wei Liou, Hui-Chun Yang, Yu-Yun Peng, Keng-Chu Lin
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Patent number: 9659811Abstract: A method of forming a semiconductor device includes forming a low-k dielectric layer over a substrate and forming a first dielectric layer on the low-k dielectric layer. A first metal hard mask layer is formed on the first dielectric layer, and a second dielectric layer is formed on the first metal hard mask layer. A second metal hard mask layer is formed on the second dielectric layer, and a first trench opening is formed in the second metal hard mask layer and the second dielectric layer exposing the first metal hard mask layer. A first via opening is formed in the exposed first metal hard mask layer in the first trench opening, and the first trench opening and first via opening are extended into the low-k dielectric layer to form a first trench and a first via.Type: GrantFiled: July 7, 2016Date of Patent: May 23, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Yun Peng, Chung-Chi Ko, Shing-Chyang Pan
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Patent number: 9564383Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.Type: GrantFiled: June 8, 2015Date of Patent: February 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Joung-Wei Liou, Hui-Chun Yang, Yu-Yun Peng, Keng-Chu Lin
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Patent number: 9412648Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: GrantFiled: January 11, 2016Date of Patent: August 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng