Patents by Inventor Yu-Yun Peng

Yu-Yun Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10867785
    Abstract: A structure and a formation method of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a sealing layer over a sidewall of the gate stack using an atomic layer deposition process in a process chamber. The atomic layer deposition process includes alternately and sequentially introducing a first precursor gas and a second precursor gas over the sidewall of the gate stack to form the sealing layer. The second precursor gas has a different atomic concentration of carbon than that of the first precursor gas. The atomic layer deposition process also includes removing a reaction byproduct from the process chamber after the first precursor gas is introduced and before the second precursor gas is introduced. The method also includes partially removing the sealing layer to form a sealing element over the sidewall of the gate stack.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guan-Yao Tu, Yu-Yun Peng
  • Publication number: 20200273794
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate stack and a first dielectric layer over the substrate, a source/drain (S/D) region, a contact, and a via. The first dielectric layer is laterally aside and over the gate stack. The S/D region is located in the substrate on sides of the gate stack. The contact penetrates through the first dielectric layer to electrically connect to the S/D region. The via penetrates through a second dielectric layer to connect to the contact. The via includes a conductive layer and an adhesion promoter layer on sidewalls of the conductive layer. The conductive layer is in contact with the contact.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal A. Khaderbad, Keng-Chu Lin, Sung-Li Wang, Shuen-Shin Liang, Yasutoshi Okuno, Yu-Yun Peng, Chia-Hung Chu
  • Publication number: 20200273695
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a dielectric structure on a semiconductor substrate, introducing a first gas on the dielectric structure to form first conductive structures on the dielectric structure, and introducing a second gas on the first conductive structures and the dielectric structure. The second gas is different from the first gas. The method also includes introducing a third gas on the first conductive structures and the dielectric structure to form second conductive structures on the dielectric structure. The first gas and the third gas include the same metal.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal A. KHADERBAD, Keng-Chu LIN, Shuen-Shin LIANG, Sung-Li WANG, Yasutoshi OKUNO, Yu-Yun PENG
  • Patent number: 10669625
    Abstract: One or more pumping liners are provided for use in chemical vapor deposition (CVD). A pumping liner encircles a deposition chamber within which a wafer is placed and into which a precursor is introduced to form a thin film on a surface of the wafer. The pumping liner regulates a rate and uniformity at which a gas is removed from the deposition chamber, which in turn affects a duration or degree to which different portions of the wafer are exposed to the precursor. Controlling exposure of the wafer to the precursor promotes uniformity of the film formed on the wafer as well an ability to regulate the thickness of the film formed on the wafer. In an embodiment, a pumping liner has at least one of relatively small liner apertures, an increased number of liner apertures or a non-uniform distribution of liner apertures within a body of the pumping liner.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Hsiung Liu, Chun-Hao Hsu, Yu-Yun Peng, Chih-Yuan Yao, Chia-I Shen, Keng-Chu Lin
  • Publication number: 20200152450
    Abstract: A structure and a formation method of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a sealing layer over a sidewall of the gate stack using an atomic layer deposition process in a process chamber. The atomic layer deposition process includes alternately and sequentially introducing a first precursor gas and a second precursor gas over the sidewall of the gate stack to form the sealing layer. The second precursor gas has a different atomic concentration of carbon than that of the first precursor gas. The atomic layer deposition process also includes removing a reaction byproduct from the process chamber after the first precursor gas is introduced and before the second precursor gas is introduced. The method also includes partially removing the sealing layer to form a sealing element over the sidewall of the gate stack.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guan-Yao TU, Yu-Yun PENG
  • Publication number: 20200135488
    Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile film having a second tensile stress that is less than the first tensile stress or a compressive film. The first insulating film and second insulating film are formed of a same material. A metal hard mask layer is formed on the second insulating film.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Jung-Hau SHIU, Chung-Chi KO, Tze-Liang LEE, Yu-Yun PENG
  • Publication number: 20200135551
    Abstract: A method is provided. Plural semiconductor fins are formed on a substrate, and plural trenches each of which is formed between two adjacent semiconductor fins. A silicon liner layer is deposited to be conformal to the semiconductor fins and the trenches. The silicon liner layer is deposited by using a silane compound. Then, an oxide layer is deposited on the silicon liner layer to fill the trenches and cover the semiconductor fins, in which depositing the oxide layer forms water in the oxide layer. Next, a surface of the silicon liner layer is reacted with the water, so as to remove the water from the oxide layer.
    Type: Application
    Filed: October 24, 2018
    Publication date: April 30, 2020
    Inventors: I-Wen HSU, Yu-Yun PENG, An-Di SHEU, Jei-Ming CHEN
  • Publication number: 20200119184
    Abstract: A device includes a semiconductor fin and a shallow trench isolation (STI) structure. The semiconductor fin extends from a semiconductor substrate. The STI structure is around a lower portion of the semiconductor fin, and the STI structure includes a liner layer and an isolation material. The liner layer includes a metal-contained ternary dielectric material. The isolation material is over the liner layer.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun PENG, Keng-Chu LIN
  • Patent number: 10535512
    Abstract: A structure and a formation method of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate. The method also includes forming a sealing layer over a sidewall of the gate stack using an atomic layer deposition process. The atomic layer deposition process includes alternately and sequentially introducing a first silicon-containing precursor gas and a second silicon-containing precursor gas over the sidewall of the gate stack to form the sealing layer. The second silicon-containing precursor gas has a different atomic concentration of carbon than that of the first silicon-containing precursor gas. The method further includes partially removing the sealing layer to form a sealing element over the sidewall of the gate stack.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Guan-Yao Tu, Yu-Yun Peng
  • Publication number: 20200006072
    Abstract: Provided is a dielectric material composition and related methods. The method includes patterning a substrate to include a first feature, a second feature adjacent to the first feature, and a trench disposed between the first and second features. The method further includes depositing a dielectric material over the first feature and within the trench. In some embodiments, the depositing the dielectric material includes flowing a first precursor, a second precursor, and a reactant gas into a process chamber. Further, while flowing the first precursor, the second precursor, and the reactant gas into the process chamber, a plasma is formed within the process chamber to deposit the dielectric material.
    Type: Application
    Filed: April 26, 2019
    Publication date: January 2, 2020
    Inventor: Yu-Yun PENG
  • Patent number: 10515822
    Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile film having a second tensile stress that is less than the first tensile stress or a compressive film. The first insulating film and second insulating film are formed of a same material. A metal hard mask layer is formed on the second insulating film.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Yu-Yun Peng
  • Publication number: 20190385898
    Abstract: Generally, examples are provided relating to filling gaps with a dielectric material, such as filling trenches between fins for Shallow Trench Isolations (STIs). In an embodiment, a first dielectric material is conformally deposited in a trench using an atomic layer deposition (ALD) process. After conformally depositing the first dielectric material, the first dielectric material is converted to a second dielectric material. In further examples, the first dielectric material can be conformally deposited in another trench, and a fill dielectric material can be flowed into the other trench and converted.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 19, 2019
    Inventor: Yu-Yun Peng
  • Patent number: 10510895
    Abstract: A device includes a semiconductor substrate, a gate stack, and an interlayer dielectric. The gate stack is over the semiconductor substrate. The interlayer dielectric is over the semiconductor substrate and surrounds the gate stack. The interlayer dielectric includes a liner layer and a filling layer. The liner layer lines the gate stack. The filling layer is over the liner layer and includes a metal-contained ternary dielectric material.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 10510584
    Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
  • Publication number: 20190348337
    Abstract: A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material. The material may be formed using a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. The material may then be cured to remove a porogen and help to collapse channels within the material. As such, the material may be formed with a scaling factor of less than or equal to about 1.8.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 14, 2019
    Inventors: Yin-Jie Pan, Yu-Yun Peng
  • Publication number: 20190326164
    Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
  • Publication number: 20190267485
    Abstract: A device includes a semiconductor substrate, a gate stack, and an interlayer dielectric. The gate stack is over the semiconductor substrate. The interlayer dielectric is over the semiconductor substrate and surrounds the gate stack. The interlayer dielectric includes a liner layer and a filling layer. The liner layer lines the gate stack. The filling layer is over the liner layer and includes a metal-contained ternary dielectric material.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun PENG, Keng-Chu LIN
  • Patent number: 10361137
    Abstract: A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material. The material may be formed using a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. The material may then be cured to remove a porogen and help to collapse channels within the material. As such, the material may be formed with a scaling factor of less than or equal to about 1.8.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Jie Pan, Yu-Yun Peng
  • Patent number: 10340178
    Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
  • Publication number: 20190157075
    Abstract: A structure and a formation method of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate. The method also includes forming a sealing layer over a sidewall of the gate stack using an atomic layer deposition process. The atomic layer deposition process includes alternately and sequentially introducing a first silicon-containing precursor gas and a second silicon-containing precursor gas over the sidewall of the gate stack to form the sealing layer. The second silicon-containing precursor gas has a different atomic concentration of carbon than that of the first silicon-containing precursor gas. The method further includes partially removing the sealing layer to form a sealing element over the sidewall of the gate stack.
    Type: Application
    Filed: October 11, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Guan-Yao TU, Yu-Yun PENG