Abstract: An online concierge system allows users to order items within discrete time intervals later than a time when an order was received or for short-term fulfillment when the order was received. To account for a number of shoppers available to fulfill orders during different discrete time intervals and numbers of orders for fulfillment during different discrete time intervals, the online concierge system specifies a target rate for orders fulfilled later than a specified discrete time interval and a threshold from the target rate. A trained machine learning model periodically predicts a percentage of orders being fulfilled late, with an order associated with a predicted percentage when the order was received. The online concierge system increases a price of orders associated with predicted percentages greater than the threshold from the target rate. The increased price of an order is determined from a price elasticity curve and the predicted percentage.

Abstract: The present disclosure discloses a Single-Event Transient (SET) pulse measuring circuit capable of eliminating impact thereof, and an integrated circuit chip. The SET pulse measuring circuit capable of eliminating impact thereof includes four parts: a SET pulse test chain, a latch circuit, a flip-flop test circuit, a latching self-trigger circuit. The integrated circuit chip is provided with a test chain module and two sets of SET pulse measuring circuits capable of eliminating impact thereof, and inputs of the two sets of SET pulse measuring circuits capable of eliminating impact thereof are the same and each are connected to an output terminal of the test chain module.

Abstract: A method for identifying a connection slot used by a hard disk includes determining the name of a program or system kernel connected to a hard disk; determining slot information corresponding to the kernel name; generating a soft link relating the kernel name to the slot information. The soft link has a relationship with and coexists with the kernel name. A terminal device and a non-volatile storage medium therein, for performing the above-described method, are also disclosed.

Abstract: This application provides a power supply system for a motor control module and a vehicle. The power supply system includes a first current limiting unit and an isolation unit. An output end of a first direct current power supply is coupled to a first input end of the isolation unit to form a first power supply loop with the isolation unit. A first output end of a second direct current power supply is coupled to one end of the first current limiting unit. Another end of the first current limiting unit is coupled to a second input end of the isolation unit to form a second power supply loop with the isolation unit. The second power supply loop is connected in parallel to the first power supply loop.

Abstract: A display device is provided, and includes a display panel, a multi-layered polarizer layer, and a cover layer. The display panel has a substrate with two opposite first edges. The multi-layered polarizer layer is disposed on the display panel and has a bottom layer with two opposite second edges corresponding to the two opposite first edges respectively. The cover layer is disposed on the multi-layered polarizer layer. A distance between one of the two opposite first edges and one of the two opposite second edges corresponding to the one of the two opposite first edges is greater than 0 and less than or equal to 5 millimeters.

Abstract: Microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.

Abstract: Disclosed is a winding method using an air expansion structure, which accurately controls the winding process by preset inflation parameter values and preset winding parameter values, so as to create space for a membrane to contract after winding, that is, to relieve the stress of the membrane, so as to avoid the situation of deviation or innermost side wrinkling during winding of the membrane, and the rewinding procedure is not needed, so that the complexity of the working procedure is reduced.

Abstract: A semiconductor die includes a first semiconductor substrate; a first interconnect structure disposed on a front side of the first semiconductor substrate; a first through-substrate via (TSV) structure extending through the first semiconductor substrate; and a first fuse structure disposed between and electrically connecting the TSV structure and the first interconnect structure.

Abstract: The present disclosure relates to a method and apparatus for generating a quantum state preparation circuit, a quantum chip, an electronic device, a storage medium, and a computer program product. The method includes: determining a target qubit set with a binary tree restriction and applying a single qubit flip gate to a first target sub-node qubit; applying a two-qubit phase offset gate between sub-node qubits; applying a two-qubit SWAP gate between the first target sub-node qubit and a second target sub-node qubit; taking the sub-node qubits as the root node qubit and iteratively performing until the sub-node qubits are leaf node qubits; and applying the two-qubit phase offset gate with a path restriction between leaf node qubits and applying a single qubit phase offset gate to the leaf node qubits to obtain a quantum state preparation circuit.

Abstract: Embodiments of the present disclosure relate to speech tendency classification.

Abstract: The COVID-19 pandemic has led to a worldwide health crisis and devastating economic and social issues. The present invention provides a method enhancing the effectiveness of the vaccines currently used for the severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2), which comprises three incremental doses of a vaccine to elicit an enhanced immune response against in a subject. The first dose, second dose, and final dose are administered in the amount of 10-25%, 45-55%, and about 100% of the vaccine's full-strength dose, respectively.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, forming a first doped region adjacent to the STI, removing part of the STI, and then forming a first gate structure on the substrate and the STI. Preferably, the first gate structure includes a high-k dielectric layer on the substrate and a gate electrode on the high-k dielectric layer, in which the high-k dielectric layer comprises a first L-shape.

Abstract: The present disclosure is directed to workpiece support for supporting a workpiece during semiconductor processing. The workpiece support includes one or more support frame bodies including a plurality of spaced apart spacers on a first surface of the support frame bodies. The spacers include a first surface spaced apart from the first surface of the support frame body. The spacing between the first surface of the spacers and the first surface of the support frame body results in the underside of the workpiece contacting the spacers but not contacting the first surface of the support frame body. Portions of the underside of the workpiece that do not contact the first surface of the support frame body are less susceptible to damage or accumulation of unwanted debris.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, a first gate electrode, a second gate electrode, a first doped region, a second doped region, a third doped region, and a first interconnection structure. The substrate comprises a well region of a first conductive type. The first and second gate electrodes are disposed on the substrate. The first, second, and third doped regions are embedded within the well region and are of the first conductive type. The first interconnection structure electrically connects the first gate electrode and the second gate electrode. The first doped region and the second doped region are disposed on opposite sides of the first gate electrode.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a via structure. The via structure is through the substrate. The via structure includes a first conductive portion, a second conductive portion, a first barrier portion, a second barrier portion, and a third barrier portion. The first conductive portion has a ring-shaped cross section. The second conductive portion is disposed at an inner side of the first conductive portion. The second conductive portion has a ring-shaped cross section. The first barrier portion is disposed at an outer side of the first conductive portion. The second barrier portion is disposed between the first conductive portion and the second conductive portion. The third barrier portion is disposed at an inner side of the second conductive portion. At least one of the first barrier portion, the second barrier portion, or the third barrier portion includes an insulating 2D material.

Abstract: A method of forming a transducer includes depositing a first dielectric layer on a first electrode, patterning the first dielectric layer to form a plurality of first protrusions in a first region and a plurality of second protrusions in a second region, where a density of the plurality of first protrusions in the first region is different from a density of the plurality of second protrusions in the second region, and bonding the first dielectric layer to a second electrode using a second dielectric layer, where sidewalls of the second dielectric layer define a cavity disposed between the first electrode and the second electrode, and where the plurality of first protrusions and the plurality of second protrusions are disposed in the cavity.

Abstract: Depositing a side slab structure on a cladding layer before etching a supporting dielectric prevents tapering of a silicon waveguide during etching of the supporting dielectric and a substrate. For example, the side slab structure may be deposited over the silicon waveguide and the cladding layer after etching the cladding layer. As a result, when an electronic device is integrated ex situ on the substrate, wave intensity and/or total internal reflection is improved, which improves an efficiency of the electronic device.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: An earphone charging system and a charging method thereof are provided. A charging circuit of an earphone device converts an output voltage provided by a charging device into a charging voltage to charge an earphone battery when the output voltage is higher than a preset voltage. The earphone device or the charging device adjusts the output voltage to switch between a first voltage and a second voltage, so as to perform data transmission between the earphone device and the charging device, wherein the first voltage and the second voltage are higher than the preset voltage.

Abstract: A power-adjusting method for uplink transmission is provided. The power-adjusting method is applied to user equipment (UE). In response to the UE transmitting a first packet carrying a specific message to a network node, the power-adjusting method includes the UE increasing the transmission power to transmit the first packet.