Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.

Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.

Abstract: A method forming sidewall spacers on a semiconductor substrate without using the conventional plasma etching method is disclosed. In the method, a semiconductor substrate that has a gate structure formed on a top surface is first provided, followed by the deposition of a dielectric material layer on top of the semiconductor substrate. The substrate is then rotated to a rotational speed of at least 50 rpm, and an acid vapor is flown onto the substrate until the sidewall spacers are formed. The dielectric material layer for forming the sidewall spacers may be SiO2, SiON or Si3N4. The acid vapor utilized may be formed from an acid of HF, H3PO4, H2SO4 or HCl. In a preferred embodiment, the semiconductor substrate may be rotated to a rotational speed between about 100 rpm and about 150 rpm for a time period between about 10 sec. and about 20 sec.

Abstract: A method for bonding inner leads of a film substrate such as TAB or COF to bond pads of an IC die without bumps and the structure formed by the method are described. In the method, a base film is first provided which has a plurality of inner leads formed of a trapezoidal cross-section for self-aligning to a plurality of openings in a tapered shape on top of bond pads on the IC die. The inner leads have a larger thickness than the thickness of the opening over the bond pad to afford an intimate contact between the inner leads and the bond pads during a bonding process in a thermal bonder under heat and pressure, or optionally, under heat, pressure and vibration.

Abstract: A dual-panel active matrix organic electroluminescent display comprises an organic electroluminescent display panel, an active matrix panel, and a conducting and adhesive material between these two panels. The organic electroluminescent display panel and the active matrix panel are fabricated separately and then adhered and bonded together. Therefore, the layout portion of a polycrystalline-silicon TFT can be increased. If a heat and pressure adhering method is used to bond the two panels, a transparent light-conducting region is not required for the pixels on the active matrix panel. If a UV light exposure adhering method is used, only a small transparent region is reserved for UV light curing. As a result, the lighting area of the organic electroluminescent display is almost 100%.

Abstract: A method for bonding inner leads of a film substrate such as TAB or COF to bond pads of an IC die without bumps and the structure formed by the method are described. In the method, a base film is first provided which has a plurality of inner leads formed of a trapezoidal cross-section for self-aligning to a plurality of openings in a tapered shape on top of bond pads on the IC die. The inner leads have a larger thickness than the thickness of the opening over the bond pad to afford an intimate contact between the inner leads and the bond pads during a bonding process in a thermal bonder under heat and pressure, or optionally, under heat, pressure and vibration.

Abstract: A method for simultaneously forming a flat display panel and bonding to a printed circuit board is disclosed in which a silicon wafer is first supplied and then coated with an alignment layer, a multiplicity of spacers are then mounted to the wafer before it is severed into a multiplicity of dies. A frame seal is then applied to the periphery of the die, while a multiplicity of metal leads is formed on the die for electrical communication with a multiplicity of thin film transistors. A glass plate is then assembled to the silicon substrate by the frame seal, while simultaneously bonded to a printed circuit board in a bonder apparatus under pressure by utilizing a conductive material such as silver paste, an anisotropic conductive film or an isotropic conductive adhesive.

Abstract: An apparatus and a method for etching a plurality of glass panels are disclosed. The apparatus is constructed by mounting a panel holder in an etch tank equipped with a rotating means for rotating the panel holder during the etching process. The panel holder is adapted for receiving a plurality of glass and mounting the panels in a vertical position with at least two edges of the panels mounted in a plurality of tracks for protecting conductive elements formed on the edges of the panels and also for holding the panels securely during the rotation of the panel holder. The method for etching the panels can be carried about at a rotational speed between about 5 rpm and about 60 rpm in an etchant solution of a diluted acid such as HF having a concentration of at least 5 vol. %. A suitable immersing time for the plurality of glass panels in the diluted etchant for producing panels of smaller thicknesses is at least 3 min.

Abstract: A method for simultaneously forming a flat display panel and bonding to a printed circuit board is disclosed in which a silicon wafer is first supplied and then coated with an alignment layer, a multiplicity of spacers are then mounted to the wafer before it is severed into a multiplicity of dies. A frame seal is then applied to the periphery of the die, while a multiplicity of metal leads is formed on the die for electrical communication with a multiplicity of thin film transistors. A glass plate is then assembled to the silicon substrate by the frame seal, while simultaneously bonded to a printed circuit board in a bonder apparatus under pressure by utilizing a conductive material such as silver paste, an anisotropic conductive film or an isotropic conductive adhesive.

Abstract: A process for forming a low resistance, titanium silicide layer, for use as a component of a narrow width, polycide gate structure, has been developed. The process features a combination of ion implantation procedures, performed prior to, and after, titanium deposition. The combination of ion implantation procedures restricts excessive movement of silicon, from a polysilicon gate structure, as well as from a source/drain region, into the forming titanium silicide layer, during subsequent anneal cycles used to form the titanium silicide layer. The ability to limit the amount of silicon, in the titanium silicide layer, allows a low resistance, titanium silicide layer to be used for polycide gate structures, with a width narrower than 0.20 micrometers.

Abstract: A method for removing residual photoresist and polymer residues from silicon wafers after a polysilicon plasma etch with minimal gate oxide loss is described. The method is particularly useful for cleaning wafers after polysilicon or polycide gate etching in MOSFET with when very thin gate oxides (<100Å). In order to etch the final portion of the polysilicon gate structure including an over etch to removed isolated polysilicon patches, an etchant containing HBr is used to provide a high polysilicon to gate oxide selectivity. This etch component causes a polymer veil to form over the surface of the photoresist which is difficult to remove except by aqueous etchants which also cause significant gate oxide loss. The method of the invention addresses the removal of the veil polymer, the photoresist, and a sidewall polymer by an all dry etching process.

Abstract: A process for forming a low resistance, titanium disilicide layer, on regions of a MOSFET device, has been developed. The process features the deposition of a capping, silicon oxide layer, on first phase, high resistance, titanium disilicide regions. The capping, silicon oxide layer, featuring a compressive stress, reduces the risk of titanium disilicide regions, formed with a tensile stress, from adhesion loss, or peeling, from underlying regions of the MOSFET device, such as from the top surface of a narrow width, polysilicon gate structure. In addition the capping silicon oxide layer protects underlying titanium disilicide regions from the ambient used during the anneal cycle used to convert the first phase, high resistance, titanium disilicide region, to the second phase, low resistance, titanium disilicide region.

Abstract: The present invention provides a method for monitoring a self-aligned contact (SAC) etching process. A wafer with an oxide layer serves as an oxide control wafer. The oxide layer is formed on the substrate. The oxide control wafer and a SAC wafer with SAC structure are simultaneously treated with a SAC etching process in an etching chamber with the same etching recipe. A contact hole is formed by etching the oxide layer of the oxide control wafer after the SAC etching process. The depth of a profile transition point and the depth of etching stop for the oxide control wafer can be observed by cross-section SEM. The profile transition depth in the oxide control wafer corresponds to the etching thickness of SiN corner loss in the SAC wafer. Therefore, the profile transition depth and the depth of etching stop in the oxide control wafer can be used to monitor the etching chamber condition.

Abstract: A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.

Abstract: A method of etching polysilicon using an oxide hard mask using a three step etch process. Steps one and two are performed insitu in a high density plasma (e.g., TCP--transformer coupled plasma) oxide etcher. Step 3, the polysilicon etch is performed in a different etcher (e.g., poly RIE etcher). A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30.

Abstract: An improved and new method for forming a metal conductor interconnection structure on a semiconductor substrate containing DRAM devices has been developed. The method utilizes a thermal anneal in a flowing gas mixture of nitrogen and hydrogen following patterning of the metal conductor interconnection structure and results in DRAM devices having improved mean refresh time (time between refresh cycles).

Abstract: The present invention is a method for reducing particles during the manufacturing of fin or cylinder capacitors on a wafer. This invention utilizes a negative photoresist wafer edge exposure process to protect the edge of a wafer. This prevents polysilicon peeling from the edge of the wafer so as to reduce the defects and particles appearing on the wafer.

Abstract: A new method of metallization using a dimple free tungsten plug is described. An insulating layer is deposited overlying semiconductor device structures. An opening is etched through the insulating layer to contact one of the semiconductor device structures. A layer of tungsten is deposited overlying the insulating layer and within the opening. A photoresist block is formed on the tungsten layer over the contact opening. The photoresist block is a reverse pattern of the photoresist layer used to define the opening in the insulating layer. The tungsten layer is partially etched forming a mound in the tungsten layer under the photoresist block and over the opening. The photoresist block is removed and the remaining tungsten layer is etched again resulting in the formation of a dimple free tungsten plug with a planar surface.

Abstract: A method for making improved capacitor bottom electrodes (capacitor nodes) having longer refresh cycle times and increased capacitance for DRAM cells has been achieved. The method involves using a polysilicon high-temperature film (HTF) instead of the conventional doped polysilicon to form the node capacitors. After forming the DRAM pass transistors (FETs) and depositing an insulating layer, node contact openings are etched in the insulator to the drain of the FET. The capacitor bottom electrodes are formed by depositing a polysilicon HTF at a temperature of at least 650.degree. C. using a reactant gas mixture of H.sub.2 /SiH.sub.4 /PH.sub.3, which results in a longer refresh cycle time and increased capacitance. This results in a significantly improved final die yield. After forming an interelectrode dielectric layer on the bottom electrodes, another doped polysilicon layer is deposited to form the top electrodes to complete the DRAM cells.

Abstract: The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specially designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas.