Abstract: A field oxide region and method of forming a field oxide region using a LOCOS process and nitride spacers formed on the sidewalls of the field oxide regions. During the LOCOS process recesses are formed in the field oxide which result in poor step coverage during successive process steps. Nitride spacers are formed on the sidewalls of the field oxide covering the recesses. The spacers provide a smooth surface over the field oxide and improved step coverage during subsequent process steps.

Abstract: A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.

Abstract: A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereupon a blanket target layer. Formed upon the blanket target layer is a blanket focusing layer, where the blanket focusing layer is formed from an organic material and where the blanket focusing layer is susceptible to a reproducible negative etch bias within a first etch method employed in etching the blanket focusing layer to form a patterned focusing layer. There is then formed upon the blanket focusing layer a blanket photoresist layer which is photoexposed and developed to form a patterned photoresist layer. There is then etched through the first etch method the blanket focusing layer to form the patterned focusing layer while employing the patterned photoresist layer as a first etch mask layer. The patterned focusing layer so formed has the reproducible negative etch bias with respect to the patterned photoresist layer.

Abstract: A planarization process, featuring removal of spin on glass, used to fill narrow spaces between metal lines, has been developed. A dual dielectric, of underlying silicon oxide, and overlying silicon nitride, are initially used to passivate the metal lines, followed by the spin on glass fill. A RIE etchback of the spin on glass proceeds to a point in which the silicon nitride, on the metal line, is exposed. The exposed silicon nitride is then removed leaving a silicon oxide passivated metal line, and seamless insulator filled spaces. The ability of not exposing the passivating silicon oxide to RIE echback process, allows seamless fills to result.

Abstract: A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket target layer. There is then formed upon the blanket target layer a blanket focusing layer, where the blanket focusing layer is formed of an organic anti-reflective coating (ARC) material which is susceptible to a reproducible positive taper within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer. The first etch method is a first plasma etch method employing an etchant gas composition comprising carbon tetrafluoride and argon. There is then formed upon the blanket focusing layer a blanket photoresist layer. The blanket photoresist layer is then photoexposed and developed layer to form a patterned photoresist layer.

Abstract: A process has been developed in which seamless tungsten plugs are used to fill deep, narrow contact holes. The process features initially forming a tungsten plug in a contact hole, via tungsten LPCVD processing, followed by an RIE etch back, and recessing process. A second tungsten LPCVD procedure is then used to fill seams or defects in the underlying tungsten plug. Another RIE etch back procedure is then employed to create a seamless, composite tungsten plug structure, in the deep, narrow contact hole.

Abstract: The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specifically designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas.

Abstract: A method for improving the etch back uniformity of a SOG layer by removing an etch back resistant polymer which builds up on the SOG layer during the etch back process. According to the present invention, a first insulation layer and a SOG layer are formed on a substrate. The SOG layer is partially etched back in a fluorocarbon containing plasma which forms a polymer residue on the SOG layer surface. The SOG layer is then treated in situ with an oxygen containing plasma to remove any of the etch resistant polymer residue on the SOG layer surface. The above in situ etch and oxygen containing plasma treatment of the spin-on-glass layer are repeated until the SOG layer is etched back to the desired thickness.

Abstract: A new method of metallization using a dimple-free tungsten plug is described. Semiconductor device structures are formed in and on a semiconductor substrate. An insulating layer is deposited overlying the semiconductor device structures. An opening is etched through the insulating layer to contact one of the semiconductor device structures. A layer of tungsten is deposited overlying the insulating layer and within the opening. The tungsten layer is coated with a layer of spin-on-glass wherein the spin-on-glass layer planarizes the top surface of the substrate. The spin-on-glass and tungsten layers are etched back leaving the tungsten layer only within the opening as a tungsten plug wherein the presence of the spin-on-glass layer overlying the tungsten layer prevents the formation of a dimple within the tungsten plug completing the formation of the dimple-free tungsten plug in the fabrication of an integrated circuit.

Abstract: This invention provides a method of cleaning integrated circuit wafers which effectively removes precipitates formed as a result of the tungsten etchback process. When tungsten is used to fill via holes in an inter-metal dielectric layer an adhesion layer of titanium nitride, TiN, is required to provide good adhesion. As a result of the tungsten etchback, wherein fluorine based etchants are used, precipitates of TiF.sub.3 can form which are extremely difficult to remove. Methods, such as in-situ bake after the tungsten etchback, are used to prevent the formation of the precipitates but do not remove them after they are formed. This invention teaches a method using a strong oxidizing agent, such as H.sub.2 O.sub.2, to cause an oxidation-reduction reaction which converts the precipitates to a water soluble form. The water soluble form of the precipitates are then removed using a water rinse and spin dry process.

Abstract: A method of cleaning an electrostatic chuck, wherein a soft, particle adherent, sheet of material is affixed to a dummy wafer. The dummy wafer is then placed on the electrostatic chuck, and DC power applied to the chuck electrode to build up an electrostatic force between the chuck and wafer. After the power is turned off, the wafer and sheet of material with the adhered particle contamination is removed.

Abstract: A method of fabrication of a DRAM cell, which forms an improved smooth top cylinder surface and provides controllable cylinder height. A semiconductor structure is provided having a transistor. Also provided are a barrier layer 12 over a first insulating layer 11 on the semiconductor structure. A polysilicon plug 14 extends through the barrier layer 12 and the insulating layer 11. A second insulating layer 16 is formed over portions of the barrier layer 12 and has an opening over the polysilicon plug 14 and over portions of the barrier layer adjacent to the polysilicon plug 14. A polysilicon layer 18 is formed over the second insulating layer 16, the sidewalls of the second insulating layer 16, the portions of the barrier layer 12 adjacent to the polysilicon plug 14 and over the polysilicon plug 14. A gap filling third insulating layer 20 is formed over the polysilicon layer 18.

Abstract: This invention provides a method for removing metal etch residue of silicon nodules, resulting from a small percentage of silicon in the metal, without causing overetch damage to the photoresist pattern, the metal electrode pattern, or to dielectric layers. The metal conductor layer is partially etched leaving from 20 to 80 percent of the original thickness. Any residue of silicon nodules formed during this partial etching is then removed using ion bombardment. The remainder of the metal conductor layer is then etched. A short overetch period is used to remove any remaining residue of silicon nodules. The overetch period is short and there is no deterioration of the photoresist or exposed edges of the electrode pattern.

Abstract: A novel method for improving the etch back uniformity for inter-metal-dielectric planarization was accomplished. Conventional single etch backs use a high polymer chemistry gas mixture (CF.sub.4 /CHF.sub.3) to etch back the planar spin-on-glass (SOG) layer to a conformal insulating barrier layer over a patterned metal. The polymer producing etch gas eliminates micro-loading effects by providing the required selectivity (about 1.6) between the insulating barrier layer and SOG for good planarization, but results in poor etch back uniformity (about 12 to 15%) across the wafer when the SOG is etched. The improved method, of this invention, uses a partial first etch back in a downstream etcher using CF.sub.4 /O.sub.2 having a etch rate that decreases from center to edge of wafer, thereby forming a convex SOG etch rate profile. The remaining SOG layer is then etched to the insulating barrier layer in the CF.sub.4 /CHF.sub.3 etch gas having an etch rate that increases from center to edge of wafer.

Abstract: A method for forming a sacrificial planarization layer over an SOG layer which provide a more planar final surface. A substrate is provided with a first insulating layer formed on its surface. A spin-on-glass (SOG) layer is formed over the first insulating layer. The SOG layer has a greater thickness towards the outer edge compared to the central area of the substrate. Next a sacrificial layer is formed over the SOG layer. The sacrificial layer, preferably formed of silicon oxide material, is formed so that the layer has a greater thickness towards the outside of the wafer than in the central area. Next, the sacrificial layer is etched away and portions of the SOG layer are etched. The etch rates of the sacrificial layer, the SOG layer and the first insulating layer are approximately equal so that the planar top SOG surface is transferred to the final top surface after the etch.

Abstract: A process for preventing the formation of precipitates on a substrate surface containing titanium after a contact layer (e.g., tungsten layer) etch back. The process involves removing the precursor chemicals of the precipitate. With the invention, the precursor are removed by baking the substrate at a temperature of approximately 120.degree. C. for approximately 80 seconds. Preferably, the baking process is performed in situ by a halogen lamp mounted on the exit loading dock of the etcher thereby not impacting the wafer throughput of the etcher.

Abstract: A process for preventing the formation of precipitates on a substrate surface after a contact layer (e.g., tungsten layer) etch back. The process involves removing the precursor chemicals of the precipitate. In one embodiment of the invention, the precursors are removed after etching contact layer by rinsing the substrate in water at about 30.degree. C. for about 10 minutes. In a second embodiment of the invention, the precursors are removed by baking the substrate at a temperature of approximately 120.degree. C. for approximately 180 seconds.

Abstract: An improved process for planarization of an integrated circuit structure having raised portions is provided. A conformal insulating layer is deposited over the structure. Next, a sacrificial dielectric layer is formed over the insulating layer. A planarization layer is formed over the dielectric layer. Then, parts of the planarization layer, dielectric layer, and insulating layer are etched to planarize said integrated circuit structure using an etch chemistry which provides for an uniform etch rate through all three layers. The sacrificial dielectric layer and the etch chemistry provide uniform etching by eliminating micro loading effects.

Abstract: A new method of metallization using a dimple-free tungsten plug is described. Semiconductor device structures are formed in and on a semiconductor substrate. An insulating layer is deposited overlying the semiconductor device structures. An opening is etched through the insulating layer to contact one of the semiconductor device structures. A layer of tungsten is deposited overlying the insulating layer and within the opening. The tungsten layer is coated with a layer of spin-on-glass wherein the spin-on-glass layer planarizes the top surface of the substrate. The spin-on-glass and tungsten layers are etched back leaving the tungsten layer only within the opening as a tungsten plug wherein the presence of the spin-on-glass layer overlying the tungsten layer prevents the formation of a dimple within the tungsten plug completing the formation of the dimple-free tungsten plug in the fabrication of an integrated circuit.