Patents by Inventor Yuan-Chang Su

Yuan-Chang Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10457837
    Abstract: The embodiments of the present disclosure provide a coating composition, including: polysilsesquioxane polymer modified organic resin represented by Formula (1): Wherein, R1 is C3-12 epoxy group, C3-12 acrylate group, C3-12 alkylacryloxy group, C3-12 aminoalkyl group, C3-12 isocyanate-alkyl group, C3-12 alkylcarboxylic acid group, C3-12 alkyl halide group, C3-12 mercaptoalkyl group, C3-12 alkyl group, or C3-12 alkenyl group; R2 is half oxygen(O1/2), hydroxyl group, C1-8 alkyl group, or C1-8 alkoxy group; R3 is halide group, C1-8 alkyl halide group, C1-8 alkoxy group, C1-12 alkyl group, or C5-20 aromatic ring; R4 is hydrogen or C1-8 alkyl group; R5 is modified or unmodified carbonyl compound moiety; n is a positive integer from 1 to 200; m is a positive integer from 10 to 500, and s is an integer from 0 to 250.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 29, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yuan-Chang Huang, Ya-I Hsu, Yi-Che Su, Wei-Cheng Tang, Shu-Yun Chien
  • Patent number: 10424547
    Abstract: A substrate for packaging a semiconductor device is disclosed. The substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer. The first dielectric layer includes a first portion adjacent to the first surface, a second portion adjacent to the second surface, and a reinforcement structure between the first portion and the second portion. A thickness of the first portion of the first dielectric layer is different from a thickness of the second portion of the first dielectric layer.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: Chih Cheng Lee, Yuan-Chang Su
  • Patent number: 10325842
    Abstract: A substrate for packaging a semiconductor device includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer. The first patterned conductive layer includes a first portion and a second portion. Each of the first portion and the second portion is embedded in the first dielectric layer and protrudes relative to the first surface of the first dielectric layer toward a direction away from the second surface of the first dielectric layer. A thickness of the first portion of the first patterned conductive layer is greater than a thickness of the second portion of the first patterned conductive layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: June 18, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Cheng Lee, Yuan-Chang Su
  • Publication number: 20190148280
    Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.
    Type: Application
    Filed: January 14, 2019
    Publication date: May 16, 2019
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Che Lee, Ming-Chiang Lee, Yuan-Chang Su, Tien-Szu Chen, Chih-Cheng Lee, You-Lung Yen
  • Publication number: 20190088506
    Abstract: A semiconductor package includes: (1) a first die; (2) conductive pads electrically connected to the first die, and each of the conductive pads having a lower surface; (3) a package body encapsulating the first die and the conductive pads and exposing the lower surface of each of the conductive pads from a lower surface of the package body; and (4) first traces disposed on the lower surface of the package body and connected to the lower surface of each of the conductive pads, wherein a thickness of each of the first traces is less than 100 micrometers.
    Type: Application
    Filed: November 6, 2018
    Publication date: March 21, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Bernd Karl APPELT, Kay Stefan ESSIG, William T. CHEN, Yuan-Chang SU
  • Publication number: 20190080995
    Abstract: A substrate for packaging a semiconductor device includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer. The first patterned conductive layer includes a first portion and a second portion. Each of the first portion and the second portion is embedded in the first dielectric layer and protrudes relative to the first surface of the first dielectric layer toward a direction away from the second surface of the first dielectric layer. A thickness of the first portion of the first patterned conductive layer is greater than a thickness of the second portion of the first patterned conductive layer.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Cheng LEE, Yuan-Chang SU
  • Publication number: 20190067211
    Abstract: A substrate for packaging a semiconductor device is disclosed. The substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer. The first dielectric layer includes a first portion adjacent to the first surface, a second portion adjacent to the second surface, and a reinforcement structure between the first portion and the second portion. A thickness of the first portion of the first dielectric layer is different from a thickness of the second portion of the first dielectric layer.
    Type: Application
    Filed: August 30, 2017
    Publication date: February 28, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih Cheng LEE, Yuan-Chang SU
  • Patent number: 10181438
    Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: January 15, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Che Lee, Ming-Chiang Lee, Yuan-Chang Su, Tien-Szu Chen, Chih-Cheng Lee, You-Lung Yen
  • Patent number: 10128198
    Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: November 13, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Chih-Cheng Lee, Yuan-Chang Su
  • Patent number: 10096542
    Abstract: A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is embedded in the first dielectric structure, and does not protrude from a first surface of the first dielectric structure. The second dielectric structure is disposed on the first surface of the first dielectric structure. The second circuit layer is embedded in the second dielectric structure, and is electrically connected to the first circuit layer. A first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, and a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: October 9, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih Cheng Lee, Yuan-Chang Su
  • Patent number: 10083902
    Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: September 25, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Chang Su, Chih-Cheng Lee, Cheng-Lin Ho
  • Patent number: 10079156
    Abstract: The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a component within the encapsulation layer, a first dielectric layer, a second dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The component includes pads on a front surface of the component. The first dielectric layer is disposed on a surface of the encapsulation layer. The second dielectric layer is disposed on a surface of the first dielectric layer. The first and second dielectric layers define via holes extending from the second dielectric layer to respective ones of the pads. The first patterned conductive layer is disposed within the first dielectric layer and surrounds the via holes. The second patterned conductive layer is disposed within the second dielectric layer and surrounds the via holes.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: September 18, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Cheng Lee, Yuan-Chang Su, Yu-Lin Shih, You-Lung Yen
  • Publication number: 20180240743
    Abstract: A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is embedded in the first dielectric structure, and does not protrude from a first surface of the first dielectric structure. The second dielectric structure is disposed on the first surface of the first dielectric structure. The second circuit layer is embedded in the second dielectric structure, and is electrically connected to the first circuit layer. A first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, and a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 23, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih Cheng LEE, Yuan-Chang SU
  • Publication number: 20170229402
    Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: You-Lung YEN, Chih-Cheng LEE, Yuan-Chang SU
  • Patent number: 9659853
    Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: May 23, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Chih-Cheng Lee, Yuan-Chang Su
  • Patent number: 9583427
    Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: February 28, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Cheng Lee, Yuan Chang Su, Cheng-Lin Ho, Chung-Ming Wu, You-Lung Yen
  • Patent number: 9564346
    Abstract: A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 7, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen
  • Publication number: 20160322292
    Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.
    Type: Application
    Filed: July 12, 2016
    Publication date: November 3, 2016
    Inventors: Yuan-Chang SU, Chih-Cheng LEE, Cheng-Lin HO
  • Publication number: 20160315041
    Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.
    Type: Application
    Filed: April 24, 2015
    Publication date: October 27, 2016
    Inventors: You-Lung YEN, Chih-Cheng LEE, Yuan-Chang SU
  • Publication number: 20160240469
    Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.
    Type: Application
    Filed: April 25, 2016
    Publication date: August 18, 2016
    Inventors: Chih-Cheng LEE, Yuan Chang Su, Cheng-Lin Ho, Chung-Ming Wu, You-Lung Yen