Patents by Inventor Yuan-Chang Su

Yuan-Chang Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100288541
    Abstract: A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate.
    Type: Application
    Filed: September 18, 2009
    Publication date: November 18, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bernd Karl APPELT, William T. CHEN, Calvin CHEUNG, Shih-Fu HUANG, Yuan-Chang SU, Chia-Cheng CHEN, Ta-Chun LEE
  • Publication number: 20100289132
    Abstract: A substrate having single patterned metal layer applied in a package is provided. The substrate includes a first patterned dielectric layer, a patterned metal layer and a second patterned dielectric layer, wherein the patterned metal layer is embedded in the first patterned dielectric layer. Also, the top surfaces of the patterned metal layer and the first patterned dielectric layer lie in the same plane. At least part of the patterned metal layer are exposed from the holes formed on the lower surface of the first patterned dielectric layer, so as to form plural first contact pads for electrical connection downwardly. The second patterned dielectric layer, formed above the patterned metal layer and the first patterned dielectric layer, at least exposes part of the patterned metal layer to form plural second contact pads at the top surface of the patterned metal layer for electrical connection upwardly.
    Type: Application
    Filed: March 3, 2010
    Publication date: November 18, 2010
    Inventors: Shih-Fu Huang, Yuan-Chang Su, Chia-Cheng Chen, Chia-Ching Chen
  • Publication number: 20100055392
    Abstract: The present invention directs to fabrication methods of single-sided or double-sided multi-layered substrate by providing a lamination structure having at least a core structure and first and second laminate structures stacked over both surfaces of the core structure. The core structure functions as the temporary carrier for carrying the first and second laminate structures through the double-sided processing procedures. By way of the fabrication methods, the production yield can be greatly improved without increasing the production costs.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 4, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bernd Karl Appelt, Yuan-Chang Su, Ming-Chiang Lee, You-Lung Yen
  • Patent number: 6353997
    Abstract: A layer build-up process for forming a multi-layer board. A conductive substrate has a plurality of bumps formed thereon. The space between the bumps is filled with a dielectric material. The conductive substrate and a core substrate having an insulation layer and a first wiring layer on each side of the insulation layer are pressed together such that the bumps are electrically connected to one of the first wiring layer via a joining material. The conductive substrate is next patterned to form a second wiring layer such that the second wiring layer is electrically coupled to one of the first wiring layer via the bumps. The second wiring layer, the bumps and the dielectric material together constitute a composite layer unit. To obtain a multi-layer board, a multiple of the composite layer units can be formed over each side of a substrate core by repeating the above process.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: March 12, 2002
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Yuan-Chang Su