Patents by Inventor Yuan-Chen Sun
Yuan-Chen Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160005817Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a channel region comprising dopants of a first type. The MOSFET device further includes a gate dielectric over the channel region, and a gate over the gate dielectric. The MOSFET device further includes a source comprising dopants of a second type, and a drain comprising dopants of the second type, wherein the channel region is between the source and the drain. The MOSFET device further includes a deactivated region underneath the gate, wherein dopants within the deactivated region are deactivated.Type: ApplicationFiled: September 16, 2015Publication date: January 7, 2016Inventors: Dhanyakumar Mahaveer SATHAIYA, Kai-Chieh YANG, Wei-Hao WU, Ken-Ichi GOTO, Zhiqiang WU, Yuan-Chen SUN
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Patent number: 9153662Abstract: A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device.Type: GrantFiled: March 29, 2012Date of Patent: October 6, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Dhanyakumar Mahaveer Sathaiya, Kai-Chieh Yang, Wei-Hao Wu, Ken-Ichi Goto, Zhiqiang Wu, Yuan-Chen Sun
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Patent number: 9123553Abstract: A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.Type: GrantFiled: October 7, 2011Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Shi Liu, Chen-Hua Yu, Yuh-Jier Mii, Yuan-Chen Sun
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Publication number: 20130256796Abstract: A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Dhanyakumar Mahaveer SATHAIYA, Kai-Chieh YANG, Wei-Hao WU, Ken-Ichi GOTO, Zhiqiang WU, Yuan-Chen SUN
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Publication number: 20120028441Abstract: A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.Type: ApplicationFiled: October 7, 2011Publication date: February 2, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Shi Liu, Chen-Hua Yu, Yuh-Jier Mii, Yuan-Chen Sun
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Patent number: 8048717Abstract: A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.Type: GrantFiled: April 25, 2007Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Shi Liu, Chen-Hua Yu, Yuh-Jier Mii, Yuan-Chen Sun
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Patent number: 7612364Abstract: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor comprises an impurity of a first conductivity type; and a portion of the semiconductor substrate adjoining the stressor and on an opposite side of the stressor from the gate stack, wherein the portion of the semiconductor substrate is doped with an impurity of the first conductivity type.Type: GrantFiled: November 20, 2006Date of Patent: November 3, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Kong-Beng Thei, Yuan-Chen Sun
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Publication number: 20080268573Abstract: A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.Type: ApplicationFiled: April 25, 2007Publication date: October 30, 2008Inventors: Chung-Shi Liu, Chen-Hua Yu, Yuh-Jier Mii, Yuan-Chen Sun
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Publication number: 20080185722Abstract: An integrated circuit structure having air gaps is provided. The integrated circuit includes a conductive line; a sidewall spacer on a sidewall of the conductive line, wherein the sidewall spacer comprises a dielectric material; an air-gap horizontally adjoining the sidewall spacer; and a dielectric layer on the air-gap.Type: ApplicationFiled: February 5, 2007Publication date: August 7, 2008Inventors: Chung-Shi Liu, Chen-Hua Yu, Yuh-Jier Mii, Yuan-Chen Sun
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Publication number: 20080054250Abstract: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor comprises an impurity of a first conductivity type; and a portion of the semiconductor substrate adjoining the stressor and on an opposite side of the stressor from the gate stack, wherein the portion of the semiconductor substrate is doped with an impurity of the first conductivity type.Type: ApplicationFiled: November 20, 2006Publication date: March 6, 2008Inventors: Harry Chuang, Kong-Beng Thei, Yuan-Chen Sun
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Publication number: 20080042123Abstract: An integrated circuit includes a semiconductor substrate having a first region, at least one p-type region in the semiconductor substrate having SiGe regions formed therein, and at least one n-type region in the semiconductor substrate. All SiGe regions in the first region have a first combined area. All p-type regions in the first region have a second combined area. All n-type regions in the first region have a third combined area. The ratio of the first combined area to a total area of the second combined area and the third combined area is less than about 30 percent.Type: ApplicationFiled: January 30, 2007Publication date: February 21, 2008Inventors: Kong-Beng Thei, Harry Chuang, Yuan-Chen Sun
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Patent number: 6774463Abstract: In a Field Effect Transistor (FET) with a semiconductor channel the use of a high Tc oxide superconductor material in the gate electrode provides both control of parasitic resistance and capacitance and a proper work function when operated at a temperature below the Tc. The 1-2-3 compound oxide superconductors with the general formula Y1Ba2Cu3O7-y where y is approximately 0.1 have the ability in use in FET's to provide convenient work functions, low resistance and capacitance, and to withstand temperatures encountered in processing as the FET is being manufactured.Type: GrantFiled: February 24, 1992Date of Patent: August 10, 2004Assignee: International Business Machines CorporationInventors: Praveen Chaudhari, Richard Joseph Gambino, Eti Ganin, Roger Hilsen Koch, Lia Krusin-Elbaum, Robert Benjamin Laibowitz, George Anthony Sai-Halasz, Yuan-Chen Sun, Matthew Robert Wordeman
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Patent number: 6245639Abstract: A process for fabricating a narrow channel width, MOSFET device, with a reduced reverse narrow channel effect, (RNCE), has been developed. The reduction of the level of dopant depletion, from the channel region, to the interface of a shallow trench —channel region, has been achieved via use of a large angle, nitrogen ion implantation procedure, performed to exposed surfaces of a shallow trench shape, prior to insulator fill. A nitrogen rich, silicon layer, at the shallow trench —channel interface, reduces the level of boron depletion, from the channel region, to the RIE damaged region, near the shallow trench shape.Type: GrantFiled: February 8, 1999Date of Patent: June 12, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: ChaoChieh Tsai, Yuan-Chen Sun
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Patent number: 6083824Abstract: A method of forming borderless contacts and vias is disclosed. Borders which are conventionally provided in aligning contacts and vias to device and/or metal regions in a semiconductor device take up too much valuable real estate on semiconductor substrates, and hence reduce productivity of the products. By employing a hard-mask of this invention, and a specific sequence of process steps, alignment can be achieved without the need for borders. First, a thin nitride layer is deposited on an insulating layer formed over a substructure of a substrate having device and/or metal regions. The hard-mask is patterned with metal line openings, and a photoresist layer is formed with contact or via pattern over the already patterned hard-mask. The contact/via openings are etched into the dielectric layer until the substructure is reached. The hole openings are filled plug metal and then partially etched back, leaving a plug in the hole opening.Type: GrantFiled: July 13, 1998Date of Patent: July 4, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chao-Chieh Tsai, Chin-Hsiung Ho, Yuan-Chen Sun
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Patent number: 6020255Abstract: A dual damascene process is disclosed for forming contact and via interconnects without borders. A nitride layer is first formed on a dielectric layer to function as a hard-mask. Metal line trench is first etched into the nitride layer and then into the dielectric layer. Then, a second photoresist layer is used to pattern contact or via hole over line trench opening and the dielectric layer is further etched through the line trench into the dielectric layer until the substructure of the substrate is reached. It is disclosed that by using the nitride layer as a hard-mask, the registration or alignment tolerance between the contact/via hole pattern and the metal line pattern can be relaxed substantially and not use a border as is conventionally practiced in order to assure proper registration between the patterns. The borderless interconnect is achieved by filling the composite line opening and the hole opening with metal and chemical mechanical polishing.Type: GrantFiled: July 13, 1998Date of Patent: February 1, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chao-Chieh Tsai, Chin-Hsiung Ho, Yuan-Chen Sun
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Patent number: 5801444Abstract: A low temperature annealed Cu silicide or germanide layer on the surface of a single crystalline semiconductor substrate of Si or Ge is used in interconnection metallization for integrated circuits. The Cu silicide or germanide layer is preferably formed by heating Cu deposited on a Si or Ge substrate up to about 200.degree. C. for about 30 minutes. The layer demonstrates superior (near ideal) current/voltage characteristics and can be used as a high temperature (600-800.degree. C.) stable Ohmic/Schottky contact to Si or as a Cu diffusion barrier. Additional embodiments involve a Cu layer on a Ge layer on Si substrate, a Cu layer on a Si.sub.x Ge.sub.1-x layer on a substrate, and the use of an intermediate layer of a refractory metal such as W.Type: GrantFiled: November 20, 1996Date of Patent: September 1, 1998Assignee: International Business Machines CorporationInventors: Mohamed Osama Aboelfotoh, Lia Krusin-Elbaum, Yuan-Chen Sun
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Patent number: 5780327Abstract: A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.Type: GrantFiled: April 16, 1997Date of Patent: July 14, 1998Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Louis Lu-Chen Hsu, Jack Allan Mandelman, Yuan-Chen Sun, Yuan Taur
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Patent number: 5689127Abstract: A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.Type: GrantFiled: March 5, 1996Date of Patent: November 18, 1997Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Louis Lu-Chen Hsu, Jack Allan Mandelman, Yuan-Chen Sun, Yuan Taur
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Patent number: 5461250Abstract: A dual gate thin film or SOI MOSFET device having a sufficiently thin body thickness with one or more semiconductor channel layer(s) sandwiched by semiconductor layers having a different energy band structure to automatically confine carriers to the channel layer(s) without the need for channel grading or modulation doping. Preferred embodiments employ strained layer epitaxy having Si/SiGe/Si or SiGe/Si/SiGe semiconductor layers.Type: GrantFiled: August 10, 1992Date of Patent: October 24, 1995Assignee: International Business Machines CorporationInventors: Joachim N. Burghartz, Bernard S. Meyerson, Yuan-Chen Sun
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Patent number: 5117271Abstract: This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-aligned elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device.Type: GrantFiled: December 7, 1990Date of Patent: May 26, 1992Assignee: International Business Machines CorporationInventors: James H. Comfort, Tze-Chiang Chen, Pong-Fei Lu, Bernard S. Meyerson, Yuan-Chen Sun, Denny D. Tang