Abstract: A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.

Abstract: A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.

Abstract: A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.

Abstract: A full-color LED display includes red, green and blue LED elements. A first substrate is used to form red and green LED elements which are then covered by a first passivation layer. A second substrate is bonded to the passviation layer and polished as a thin substrate layer. A blue LED element is fabricated on the thin substrate layer. The three LED elements are then covered by a second passivation layer to construct a full-color LED device. A full-color, high resolution and high brightness LED display is formed by a plurality of full-color LED devices arranged in rows and columns in a matrix form.

Abstract: A method of forming a low-temperature polysilicon, comprising steps of: providing a substrate with a surface on which a buffer layer, an amorphous silicon layer and a metal silicide layer are sequentially formed; forming a plurality of metal pads on predetermined regions of the metal silicide layer; and providing a current on the metal pads to transform the amorphous silicon layer into a polysilicon layer.

Abstract: A full-color LED display includes red, green and blue LED elements. A first substrate is used to form red and green LED elements which are then covered by a first passivation layer. A second substrate is bonded to the passviation layer and polished as a thin substrate layer. A blue LED element is fabricated on the thin substrate layer. The three LED elements are then covered by a second passivation layer to construct a full-color LED device. A full-color, high resolution and high brightness LED display is formed by a plurality of full-color LED devices arranged in rows and columns in a matrix form.

Abstract: A method of fabricating a metal plug. On a semiconductor substrate comprising a MOS device, a dielectric layer, and a via hole penetrating though the dielectric layer, a conformal titanium layer is formed on the dielectric layer and the via hole. A low temperature annealing is formed in a nitrogen environment, so that a surface of the titanium layer is transformed into a first thin titanium nitride layer. A conformal second titanium nitride layer is formed on the first thin titanium nitride layer by using collimator sputtering. A metal layer is formed and etched back on the second titanium nitride layer to form a metal plug.

Abstract: A method of manufacturing a cobalt suicide layer in the present invention has a silicon layer formation step. The silicon layer is formed at the interface between the cobalt layer and titanium layer, therefore the interface is smoother in this invention than in other conventional methods, and there are no voids formed at the interface. Moreover, consumption of the silicon can be controlled by adjusting the thickness of the silicon layer.

Abstract: The present invention relates to a method of manufacturing semiconductor components having a titanium nitride layer including the steps of providing a semiconductor substrate with a transistor including a gate and source/drain regions, depositing an insulating layer above the semiconductor substrate, etching the insulating layer to form an opening exposing the source/drain region below, depositing an ultra-thin titanium nitride layer having a grainy particulate profile and a thickness of about 0.5 nm to 2 nm around the edge and at the bottom of the opening, depositing a metallic layer over various aforementioned layers, and forming a metal silicide layer by heating the semiconductor substrate to allow the metallic layer to react with silicon on the semiconductor substrate surface.