Patents by Inventor Yuan CHU

Yuan CHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090172504
    Abstract: The Viterbi decoder is an essential module in a communication system, in which the power and the decoding latency are restricted. In the present invention, a power efficient low latency survivor memory architecture and an operating method for the Viterbi decoder are disclosed by providing a plurality of trace-forward units, a plurality of first signal selecting units, a plurality of second signal selecting units and a third signal selecting unit to reduce the power consumption by decreasing the exchange times of contents in the trace-forward units. Thus, the present invention is suitable for use in mobile communication devices which require low power consumption.
    Type: Application
    Filed: November 18, 2008
    Publication date: July 2, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Chuan Huang, Chun-Yuan Chu, An-Yu Wu
  • Publication number: 20090145754
    Abstract: A biochemical test system, a measurement device, a biochemical test strip and a method of making the same are provided. The biochemical test system includes a biochemical test strip and a measurement device. The biochemical test strip includes an insulating substrate, an electrode system disposed on the insulating substrate, and a pattern code disposed on one side of the insulating substrate. The pattern code includes N components and at least one of the N components penetrates the insulating substrate. The measurement device includes a microprocessor and a connector. The connector is coupled to the pattern code and the electrode system for receiving signals corresponding to the pattern code. The microprocessor is coupled to the connector for receiving signals from the connector.
    Type: Application
    Filed: February 28, 2008
    Publication date: June 11, 2009
    Applicant: APEX BIOTECHNOLOGY CORP.
    Inventors: Mon Wen Yang, Ching-Yuan Chu, Yueh-Hui Lin, Ming-Chang Hsu, Jui-Ping Wang, Thomas Y.S. Shen
  • Publication number: 20090145753
    Abstract: A biochemical test system, a measurement device, and a biochemical test strip are provided. The biochemical test strip includes an insulating substrate, an electrode system disposed on the insulating substrate, and an identifying unit disposed on one side of the insulating substrate. The identifying unit includes N components, and at least one of the N components includes a groove. It should be noted that the term ā€œNā€ in this specification is an integer greater than two. The measurement device includes a microprocessor and a connector, wherein the connector is coupled to the identifying unit for receiving a signal of an identification code corresponding to the identifying unit, and the microprocessor is coupled to the connector for receiving the signal from the connector.
    Type: Application
    Filed: August 27, 2008
    Publication date: June 11, 2009
    Inventors: Mon Wen Yang, Ching-Yuan Chu, Yueh-Hui Lin, Ming-Chang Hsu, Jui-Ping Wang, Thomas Y.S. Shen
  • Publication number: 20090124797
    Abstract: This invention relates to a process of stereoselectively synthesizing ?-nucleoside, e.g., 2?-deoxy-2,2?-difluorocytidine.
    Type: Application
    Filed: November 6, 2008
    Publication date: May 14, 2009
    Applicant: PharmaEssentia Corporation
    Inventors: Chi-Yuan Chu, Wei-Der Lee, Wensen Li, Chan Kou Hwang
  • Publication number: 20090078588
    Abstract: A system for electrochemical quantitative analysis is provided. The system includes a measuring apparatus having a plurality of analysis modes. Each of the analysis modes is for quantitatively analyzing different biochemical substance. The system further includes a plurality of test strips. Each of the test strips has a different identification component for a different analysis mode. When one of the plurality of test strips is selected to electronically connect to the measuring apparatus, the measuring apparatus executes one of the plurality of analysis modes according to the identification component of the selected test strip to quantitatively analyze a corresponding biochemical substance.
    Type: Application
    Filed: September 21, 2008
    Publication date: March 26, 2009
    Applicant: APEX BIOTECHNOLOGY CORP.
    Inventors: Yueh-Hui Lin, Guan-Ting Chen, Te-Ho Chen, Ching-Yuan Chu, Jui-Ping Wang, Cheng Allen Chang, Thomas Y.S. Shen
  • Patent number: 7441138
    Abstract: When receiving request commands from different hosts, a data system generates corresponding phase control signals and access signals based on the formats of each request command. Based on the phase control signals, timing signals corresponding to respect request commands and including a plurality of enabling time slots are generated in a way that only one timing signal includes an enabling time slot at a certain point of time. Next, an access control signal is outputted to a storage device during the enabling time slot of a corresponding timing signal. Therefore, the storage device only needs to respond to one request command at a certain point of time, and multiple data access can be effectively controlled in the data system.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: October 21, 2008
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Sheng-Yuan Chu, Ching-Wen Lai
  • Publication number: 20080168244
    Abstract: The present invention relates to a method for updating an image file that is performed by a server, when a workable image file pre-stored in a storage unit of said server needs to be updated by a new image file, that duplicates said workable image file to said storage unit as a backup image file, and then restarts said serve by invoking the operating system with said new image file, and if an operating system can not be successfully invoked with said new image file, said server automatically selects said backup image file to invoke the operating system and restore to the status before said update.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 10, 2008
    Applicant: INVENTEC CORPORATION
    Inventors: Chi-Yuan Chu Chen, Tsung-Pin Wang
  • Publication number: 20080129099
    Abstract: A seat reclining mechanism for a power wheelchair implements an actuator and a plurality of linkages mechanistically connected to the seat portion, back portion, arm rests and footrests of the wheelchair to recline the back portion and shift the seat in harmony with the center-of-gravity position of the wheelchair it attached to synchronously. So that a user can be free from the risk of falling during operation of the seat reclining mechanism.
    Type: Application
    Filed: December 4, 2006
    Publication date: June 5, 2008
    Inventors: Alfred Huang, Shun-Yuan Chu
  • Patent number: 7374956
    Abstract: A method for preserving semiconductor feature opening profiles for metrology examination including providing semiconductor wafer having a process surface comprising semiconductor feature openings; blanket depositing over the semiconductor feature openings to substantially fill the semiconductor feature openings at least one layer of material comprising silicon oxide; and, preparing a portion of the semiconductor wafer in cross sectional layout for metrology examination.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: May 20, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd
    Inventors: Shyeu Sheng Lu, Hong Yuan Chu, Kuei Shun Chen, Hua Tai Lin
  • Publication number: 20080041719
    Abstract: A liquid and a gas is constantly filled into a target chamber of a target. Then the liquid and the gas flow around the chamber and are flown out. By doing so, the target is effectively cooled down.
    Type: Application
    Filed: August 9, 2006
    Publication date: February 21, 2008
    Applicant: ATOMIC ENERGY COUNCIL-INSTITUTE OF NUCLEAR ENERGY RESEARCH
    Inventors: Wuu-Jyh Lin, Mao-Hsung Chang, Ping-Yen Huang, Jenn-Tzong Chen, Ting-Shien Duh, Dow-Che Chen, Kuo-Yuan Chu
  • Publication number: 20080012817
    Abstract: A driving method for a display panel generates AC-converting signals by setting pin levels of a driving circuit. Data pins of a driving circuit operating in a common mode are set according to a frequency-dividing ratio. Based on a line latch pulse signal and the data pins of the driving circuit operating in common mode, a corresponding AC-converting signal is generated and sent to another driving circuit operating in segment mode or common mode.
    Type: Application
    Filed: October 16, 2006
    Publication date: January 17, 2008
    Inventors: I-Min Chen, Feng-Jung Kuo, Sheng-Yuan Chu, Way-Guo Tseng
  • Publication number: 20070277006
    Abstract: When receiving request commands from different hosts, a data system generates corresponding phase control signals and access signals based on the formats of each request command. Based on the phase control signals, timing signals corresponding to respect request commands and including a plurality of enabling time slots are generated in a way that only one timing signal includes an enabling time slot at a certain point of time. Next, an access control signal is outputted to a storage device during the enabling time slot of a corresponding timing signal. Therefore, the storage device only needs to respond to one request command at a certain point of time, and multiple data access can be effectively controlled in the data system.
    Type: Application
    Filed: August 17, 2006
    Publication date: November 29, 2007
    Inventors: Sheng-Yuan Chu, Ching-Wen Lai
  • Patent number: 7247247
    Abstract: A selective etching method with lateral protection function is provided. The steps includes: (a) providing a substrate; (b) forming a plurality of tunnels; (c) forming a lateral strengthening structure at a peripheral wall of the tunnels; (d) removing a bottom portion of the lateral strengthening structure, and a part of the substrate by an etching process so as to form a lower structure and expose an unstrengthened structure; and (f) etching the unstrengthened structure laterally so as to form an upper structure.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: July 24, 2007
    Assignee: Walsin Lihwa Corporation
    Inventors: Jerwei Hsieh, Huai-Yuan Chu, Julius Ming-Lin Tsai, Weileun Fang
  • Patent number: 7088030
    Abstract: A high-aspect-ratio-microstructure (HARM) is provided. The structure includes: a substrate; a lower structure with a comb shape fixedly mounted on said substrate and having first plural comb fingers, wherein each of the first plural comb fingers has a thin slot thereon; an upper structure with a comb shape having second plural comb fingers, wherein the lower structure and the upper structure have a height difference therebetween so as to form an uneven surface; and a lateral strengthening structure formed at vertically peripheral walls of the first plural comb fingers and the second plural comb fingers for protecting the plural first and second comb fingers.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: August 8, 2006
    Assignee: Walsin Lihwa Corporation
    Inventors: Jerwei Hsieh, Huai-Yuan Chu, Julius Ming-Lin Tsai, Weileun Fang
  • Publication number: 20050263891
    Abstract: A damascene structure for semiconductor devices is provided. In an embodiment, the damascene structure includes trenches formed over vias that electrically couple the trenches to an underlying conductive layer such that the trenches have varying widths. The vias are lined with a first barrier layer. The first barrier layers along the bottom of vias are removed such that a recess formed in the underlying conductive layer. The recesses formed along the bottom of vias are such that the recess below narrower trenches is greater than the recess formed below wider trenches. In another embodiment, a second barrier layer may then be formed over the first barrier layer. In this embodiment, a portion of the conductive layer may be interposed between the first barrier layer and the second barrier layer.
    Type: Application
    Filed: April 7, 2005
    Publication date: December 1, 2005
    Inventors: Bih-Huey Lee, Hong-Yuan Chu, Ping-Kun Wu, Ching-Wen Lu, Jing-Cheng Lin, Shau-Lin Shue, Shing-Chyang Pan
  • Patent number: 6866988
    Abstract: A new and improved method for measuring dimensions of a photoresist pattern profile on a wafer substrate during photolithography for the fabrication of integrated circuits on the substrate. According to one embodiment, the method includes fixing the photoresist pattern profile on the substrate using a spin-on glass (SOG) procedure. In another embodiment, the method includes fixing the photoresist pattern profile on the substrate using a sputter oxide (SO) procedure. The fixed photoresist pattern is then subjected to a microscopy procedure, typically transmission electron microscopy (TEM), to measure the exact linewidth and other dimensions of the profile. The method prevents distortion of the profile during fixation and facilitates an accurate determination of the profile dimensions.
    Type: Grant
    Filed: October 5, 2002
    Date of Patent: March 15, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyue-Sheng Lu, Hong-Yuan Chu, Kuei-Shun Chen, Hua-Tai Lin
  • Publication number: 20040232502
    Abstract: A high-aspect-ratio-microstructure (HARM) is provided. The structure includes: a substrate; a lower structure with a comb shape fixedly mounted on said substrate and having first plural comb fingers, wherein each of the first plural comb fingers has a thin slot thereon; an upper structure with a comb shape having second plural comb fingers, wherein the lower structure and the upper structure have a height difference therebetween so as to form an uneven surface; and a lateral strengthening structure formed at vertically peripheral walls of the first plural comb fingers and the second plural comb fingers for protecting the plural first and second comb fingers.
    Type: Application
    Filed: May 6, 2004
    Publication date: November 25, 2004
    Applicant: Walsin Lihwa Corporation
    Inventors: Jerwei Hsieh, Huai-Yuan Chu, Julius Ming-Lin Tsai, Weileun Fang
  • Publication number: 20040232110
    Abstract: A selective etching method with lateral protection function is provided. The steps includes: (a) providing a substrate; (b) forming a plurality of tunnels; (c) forming a lateral strengthening structure at a peripheral wall of the tunnels; (d) removing a bottom portion of the lateral strengthening structure, and a part of the substrate by an etching process so as to form a lower structure and expose an unstrengthened structure; and (f) etching the unstrengthened structure laterally so as to form an upper structure.
    Type: Application
    Filed: May 6, 2004
    Publication date: November 25, 2004
    Applicant: Walsin Lihwa Corporation
    Inventors: Jerwei Hsieh, Huai-Yuan Chu, Julius Ming-Lin Tsai, Weileun Fang
  • Patent number: 6812156
    Abstract: A method of reducing particulate contamination in a deposition process including providing a semiconductor wafer having a process surface for depositing a deposition layer thereover according to one of a physical vapor deposition (PVD) and a chemical vapor deposition (CVD) process; depositing at least a portion of the deposition layer over the process surface; cleaning the semiconductor wafer including the process surface according to an ex-situ cleaning process to remove particulate contamination including at least one of spraying and scrubbing; and, repeating the steps of depositing and cleaning at least once to include reducing a level of occluded particulates.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: November 2, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Dyson Day, Mei-Yen Li, Ming-Te More, Hsing-Yuan Chu
  • Patent number: 6767831
    Abstract: A method for forming salicides with reduced junction leakage including providing a semiconductor process wafer comprising a silicon substrate; inducing amorphization within the silicon substrate to a form a first amorphous region having a first predetermined depth measured from the silicon substrate surface; carrying out at least one first thermal annealing process to controllably partially recrystallize the first amorphous region to produce a second amorphous region having a second predetermined depth less than the first predetermined depth; depositing a metal layer over selected areas of the silicon substrate comprising the second amorphous region; and, carrying out at least one second thermal annealing process to form a metal silicide.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: July 27, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Yuan Chu, Chih-Jian Chen