Abstract: A polycrystalline silicon wafer is provided. The polycrystalline silicon wafer, includes a plurality of silicon grains, wherein the carbon content of the polycrystalline silicon wafer is greater than 4 ppma, and the resistivity of the polycrystalline silicon wafer is greater than or equal to 1.55 ?-cm.

Abstract: An N-type polysilicon crystal, a manufacturing method thereof, and an N-type polysilicon wafer are provided. The N-type polysilicon crystal has a slope of resistivity and a slope of defect area percentage. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to resistivity presented by a unit of Ohm·cm (?·cm), the slope of resistivity is 0 to ?1.8 at the solidified fraction of 0.25 to 0.8. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to defect area percentage (%), the slope of defect area percentage is less than 2.5 at the solidified fraction of 0.4 to 0.8.

Abstract: A polycrystalline silicon column is provided. The polycrystalline silicon column includes a plurality of silicon grains grown along a crystal-growing direction. In the crystal-growing direction, the average grain size of the silicon grains and the resistivity of the polycrystalline silicon column have opposite variation in their trends, the average grain size of the silicon grains and the oxygen content of the polycrystalline silicon column have opposite variation in their trends, and the average grain size of the silicon grains and the defect area ratio of the polycrystalline silicon column have the same variation in their trends. The overall average defect area ratio of the polycrystalline silicon column is less than or equal to 2.5%.

Abstract: An N-type polysilicon crystal, a manufacturing method thereof, and an N-type polysilicon wafer are provided. The N-type polysilicon crystal has a slope of resistivity and a slope of defect area percentage. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to resistivity presented by a unit of Ohm·cm (?·cm), the slope of resistivity is 0 to ?1.8 at the solidified fraction of 0.25 to 0.8. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to defect area percentage (%), the slope of defect area percentage is less than 2.5 at the solidified fraction of 0.4 to 0.8.

Abstract: A polycrystalline silicon column is provided. The polycrystalline silicon column includes a plurality of silicon grains grown along a crystal-growing direction. In the crystal-growing direction, the average grain size of the silicon grains and the resistivity of the polycrystalline silicon column have opposite variation in their trends, the average grain size of the silicon grains and the oxygen content of the polycrystalline silicon column have opposite variation in their trends, and the average grain size of the silicon grains and the defect area ratio of the polycrystalline silicon column have the same variation in their trends. The overall average defect area ratio of the polycrystalline silicon column is less than or equal to 2.5%.

Abstract: A polycrystalline silicon wafer is provided. The polycrystalline silicon wafer, includes a plurality of silicon grains, wherein the carbon content of the polycrystalline silicon wafer is greater than 4 ppma, and the resistivity of the polycrystalline silicon wafer is greater than or equal to 1.55 ?-cm.

Abstract: A semiconductor light-emitting device includes at least one light-emitting chip. The light-emitting chip includes plural light-emitting units, which are electrically coupled to each other in series, in parallel or in series-parallel combination; a first-type electrode electrically coupled to an external power source, the first-type electrode being disposed on one of the light-emitting units; a second-type electrode disposed on another of the light-emitting units; and a tapped point for electrically coupling at least one of the light-emitting units to an electronic component.

Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.

Abstract: A semiconductor light emitting device includes a substrate and a first epitaxial structure over the substrate. The first epitaxial structure includes a first doped layer, a first light emitting layer, and a second doped layer. A first electrode is coupled to the first doped layer. A second electrode is coupled to the second doped layer facing the same direction as the first electrode. A second epitaxial structure includes a third doped layer, a second light emitting layer, and a fourth doped layer. A third electrode is coupled to the third doped layer facing the same direction as the first electrode. A fourth electrode is coupled to the fourth doped layer facing the same direction as the first electrode. An adhesive layer is between the first epitaxial structure and the second epitaxial structure.

Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.

Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.

Abstract: Methods for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current-guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a substrate) may be provided. For some embodiments, both a current-guiding structure and second current path may be provided.

Abstract: A semiconductor light-emitting device includes at least one light-emitting chip. The light-emitting chip includes plural light-emitting units, which are electrically coupled to each other in series, in parallel or in series-parallel combination; a first-type electrode electrically coupled to an external power source, the first-type electrode being disposed on one of the light-emitting units; a second-type electrode disposed on another of the light-emitting units; and a tapped point for electrically coupling at least one of the light-emitting units to an electronic component.

Abstract: An illuminating device includes at least one light-emitting source. The light-emitting source includes a substrate; at least one light-emitting chip disposed on the substrate; and at least one constant-current component electrically coupled to the light-emitting chip. The light-emitting chip includes multiple light-emitting units that are electrically coupled in series, in parallel, or in series-parallel; a first-type electrode, disposed on at least one of the light-emitting units, for electrically coupling to a central DC power source; a second-type electrode disposed on at least one light-emitting unit different from the one, on which the first-type electrode is disposed; and a tapped point configured for electrically coupling at least one of the light-emitting units to the constant-current component.

Abstract: The invention relates to a wafer-type light emitting device having a substrate, one or more light emitting semiconductors formed on the substrate, one or more frames provided over the one or more light emitting semiconductors, and one or more wavelength-converting layers applied on the one or more light emitting semiconductors and confined by the one or more frames, wherein the wafer-type light emitting device is diced into a plurality of separate light emitting units.

Abstract: The invention relates to a chip-type light emitting device including one or more light emitting semiconductors and one or more frames provided over a top of the one or more light emitting semiconductors.

Abstract: Methods for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current-guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a substrate) may be provided. For some embodiments, both a current-guiding structure and second current path may be provided.

Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.

Abstract: A semiconductor light emitting device includes a substrate and a first epitaxial structure over the substrate. The first epitaxial structure includes a first doped layer, a first light emitting layer, and a second doped layer. A first electrode is coupled to the first doped layer. A second electrode is coupled to the second doped layer facing the same direction as the first electrode. A second epitaxial structure includes a third doped layer, a second light emitting layer, and a fourth doped layer. A third electrode is coupled to the third doped layer facing the same direction as the first electrode. A fourth electrode is coupled to the fourth doped layer facing the same direction as the first electrode. An adhesive layer is between the first epitaxial structure and the second epitaxial structure.

Abstract: A semiconductor light emitting device includes a substrate, a first epitaxial structure, a first substantially transparent conducting layer, a second epitaxial structure, a second substantially transparent conducting layer, and a substantially transparent insulating layer. The first epitaxial structure is over the substrate and includes a first doped layer, a first light emitting layer, and a second doped layer. The first substantially transparent conducting layer is coupled to the second doped layer. The second epitaxial structure includes a third doped layer, a second light emitting layer, and a fourth doped layer. The second substantially transparent conducting layer is coupled to the fourth doped layer. The substantially transparent insulating layer is between the first substantially transparent conducting layer and the second substantially transparent conducting layer.