Patents by Inventor Yuan-Hsiao Chang

Yuan-Hsiao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10825940
    Abstract: A polycrystalline silicon wafer is provided. The polycrystalline silicon wafer, includes a plurality of silicon grains, wherein the carbon content of the polycrystalline silicon wafer is greater than 4 ppma, and the resistivity of the polycrystalline silicon wafer is greater than or equal to 1.55 ?-cm.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 3, 2020
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Cheng-Jui Yang, Huang Wei Lin, Yu-Min Yang, Kuo-Wei Chuang, Ming-Kung Hsiao, Yuan Hsiao Chang, Bo-Kai Wang, Wen-Huai Yu, Sung Lin Hsu, I-Ching Li, Wen-Ching Hsu
  • Patent number: 10510830
    Abstract: An N-type polysilicon crystal, a manufacturing method thereof, and an N-type polysilicon wafer are provided. The N-type polysilicon crystal has a slope of resistivity and a slope of defect area percentage. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to resistivity presented by a unit of Ohm·cm (?·cm), the slope of resistivity is 0 to ?1.8 at the solidified fraction of 0.25 to 0.8. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to defect area percentage (%), the slope of defect area percentage is less than 2.5 at the solidified fraction of 0.4 to 0.8.
    Type: Grant
    Filed: September 2, 2018
    Date of Patent: December 17, 2019
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Ching-Hung Weng, Cheng-Jui Yang, Yu-Min Yang, Yuan-Hsiao Chang, Bo-Kai Wang, Wen-Huai Yu, Ying-Ru Shih, Sung-Lin Hsu
  • Patent number: 10297702
    Abstract: A polycrystalline silicon column is provided. The polycrystalline silicon column includes a plurality of silicon grains grown along a crystal-growing direction. In the crystal-growing direction, the average grain size of the silicon grains and the resistivity of the polycrystalline silicon column have opposite variation in their trends, the average grain size of the silicon grains and the oxygen content of the polycrystalline silicon column have opposite variation in their trends, and the average grain size of the silicon grains and the defect area ratio of the polycrystalline silicon column have the same variation in their trends. The overall average defect area ratio of the polycrystalline silicon column is less than or equal to 2.5%.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: May 21, 2019
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Cheng-Jui Yang, Huang Wei Lin, Yu-Min Yang, Kuo-Wei Chuang, Ming-Kung Hsiao, Yuan Hsiao Chang, Bo-Kai Wang, Wen-Huai Yu, Sung Lin Hsu, I-Ching Li, Wen-Ching Hsu
  • Publication number: 20190096987
    Abstract: An N-type polysilicon crystal, a manufacturing method thereof, and an N-type polysilicon wafer are provided. The N-type polysilicon crystal has a slope of resistivity and a slope of defect area percentage. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to resistivity presented by a unit of Ohm·cm (?·cm), the slope of resistivity is 0 to ?1.8 at the solidified fraction of 0.25 to 0.8. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to defect area percentage (%), the slope of defect area percentage is less than 2.5 at the solidified fraction of 0.4 to 0.8.
    Type: Application
    Filed: September 2, 2018
    Publication date: March 28, 2019
    Applicant: Sino-American Silicon Products Inc.
    Inventors: Ching-Hung Weng, Cheng-Jui Yang, Yu-Min Yang, Yuan-Hsiao Chang, Bo-Kai Wang, Wen-Huai Yu, Ying-Ru Shih, Sung-Lin Hsu
  • Publication number: 20170062635
    Abstract: A polycrystalline silicon wafer is provided. The polycrystalline silicon wafer, includes a plurality of silicon grains, wherein the carbon content of the polycrystalline silicon wafer is greater than 4 ppma, and the resistivity of the polycrystalline silicon wafer is greater than or equal to 1.55 ?-cm.
    Type: Application
    Filed: August 26, 2016
    Publication date: March 2, 2017
    Applicant: Sino-American Silicon Products Inc.
    Inventors: Cheng-Jui Yang, Huang Wei Lin, Yu-Min Yang, Kuo-Wei Chuang, Ming-Kung Hsiao, Yuan Hsiao Chang, Bo-Kai Wang, Wen-Huai Yu, Sung Lin Hsu, I-Ching Li, Wen-Ching Hsu
  • Publication number: 20170058428
    Abstract: A polycrystalline silicon column is provided. The polycrystalline silicon column includes a plurality of silicon grains grown along a crystal-growing direction. In the crystal-growing direction, the average grain size of the silicon grains and the resistivity of the polycrystalline silicon column have opposite variation in their trends, the average grain size of the silicon grains and the oxygen content of the polycrystalline silicon column have opposite variation in their trends, and the average grain size of the silicon grains and the defect area ratio of the polycrystalline silicon column have the same variation in their trends. The overall average defect area ratio of the polycrystalline silicon column is less than or equal to 2.5%.
    Type: Application
    Filed: August 26, 2016
    Publication date: March 2, 2017
    Applicant: Sino-American Silicon Products Inc.
    Inventors: Cheng-Jui Yang, Huang Wei Lin, Yu-Min Yang, Kuo-Wei Chuang, Ming-Kung Hsiao, Yuan Hsiao Chang, Bo-Kai Wang, Wen-Huai Yu, Sung Lin Hsu, I-Ching Li, Wen-Ching Hsu
  • Patent number: 9190586
    Abstract: A semiconductor light-emitting device includes at least one light-emitting chip. The light-emitting chip includes plural light-emitting units, which are electrically coupled to each other in series, in parallel or in series-parallel combination; a first-type electrode electrically coupled to an external power source, the first-type electrode being disposed on one of the light-emitting units; a second-type electrode disposed on another of the light-emitting units; and a tapped point for electrically coupling at least one of the light-emitting units to an electronic component.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: November 17, 2015
    Assignee: PHOSTEK, INC.
    Inventors: Shih Tsun Yang, Yuan-Hsiao Chang, Jhih-Sin Hong
  • Patent number: 9018025
    Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: April 28, 2015
    Assignee: Phostek Inc.
    Inventor: Yuan-Hsiao Chang
  • Patent number: 8835948
    Abstract: A semiconductor light emitting device includes a substrate and a first epitaxial structure over the substrate. The first epitaxial structure includes a first doped layer, a first light emitting layer, and a second doped layer. A first electrode is coupled to the first doped layer. A second electrode is coupled to the second doped layer facing the same direction as the first electrode. A second epitaxial structure includes a third doped layer, a second light emitting layer, and a fourth doped layer. A third electrode is coupled to the third doped layer facing the same direction as the first electrode. A fourth electrode is coupled to the fourth doped layer facing the same direction as the first electrode. An adhesive layer is between the first epitaxial structure and the second epitaxial structure.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: September 16, 2014
    Assignee: Phostek, Inc.
    Inventors: Yuan-Hsiao Chang, Yi-An Lu
  • Publication number: 20140199793
    Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.
    Type: Application
    Filed: March 18, 2014
    Publication date: July 17, 2014
    Applicant: PHOSTEK INC.
    Inventor: Yuan-Hsiao CHANG
  • Patent number: 8728834
    Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: May 20, 2014
    Assignee: Phostek, Inc.
    Inventor: Yuan-Hsiao Chang
  • Patent number: 8703515
    Abstract: Methods for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current-guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a substrate) may be provided. For some embodiments, both a current-guiding structure and second current path may be provided.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: April 22, 2014
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: Wen-Huang Liu, Chen-Fu Chu, Jiunn-Yi Chu, Chao-Chen Cheng, Hao-Chun Cheng, Feng-Hsu Fan, Yuan-Hsiao Chang
  • Publication number: 20140055048
    Abstract: A semiconductor light-emitting device includes at least one light-emitting chip. The light-emitting chip includes plural light-emitting units, which are electrically coupled to each other in series, in parallel or in series-parallel combination; a first-type electrode electrically coupled to an external power source, the first-type electrode being disposed on one of the light-emitting units; a second-type electrode disposed on another of the light-emitting units; and a tapped point for electrically coupling at least one of the light-emitting units to an electronic component.
    Type: Application
    Filed: April 12, 2013
    Publication date: February 27, 2014
    Applicant: PHOSTEK, INC.
    Inventors: Shih Tsun Yang, Yuan-Hsiao Chang, Jhih-Sin Hong
  • Publication number: 20140055049
    Abstract: An illuminating device includes at least one light-emitting source. The light-emitting source includes a substrate; at least one light-emitting chip disposed on the substrate; and at least one constant-current component electrically coupled to the light-emitting chip. The light-emitting chip includes multiple light-emitting units that are electrically coupled in series, in parallel, or in series-parallel; a first-type electrode, disposed on at least one of the light-emitting units, for electrically coupling to a central DC power source; a second-type electrode disposed on at least one light-emitting unit different from the one, on which the first-type electrode is disposed; and a tapped point configured for electrically coupling at least one of the light-emitting units to the constant-current component.
    Type: Application
    Filed: April 12, 2013
    Publication date: February 27, 2014
    Applicant: Phostek, Inc.
    Inventors: Shih-Feng Shao, Yuan-Hsiao Chang, Shih Tsun Yang
  • Patent number: 8648370
    Abstract: The invention relates to a wafer-type light emitting device having a substrate, one or more light emitting semiconductors formed on the substrate, one or more frames provided over the one or more light emitting semiconductors, and one or more wavelength-converting layers applied on the one or more light emitting semiconductors and confined by the one or more frames, wherein the wafer-type light emitting device is diced into a plurality of separate light emitting units.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: February 11, 2014
    Assignee: Semileds Optoelectronics Co., Ltd.
    Inventors: Wen-Huang Liu, Yuan-Hsiao Chang, Hung-Jen Kao, Chung-Che Dan, Feng-Hsu Fan, Chen-Fu Chu
  • Patent number: 8614453
    Abstract: The invention relates to a chip-type light emitting device including one or more light emitting semiconductors and one or more frames provided over a top of the one or more light emitting semiconductors.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: December 24, 2013
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: Wen-Huang Liu, Chung-Che Dan, Yuan-Hsiao Chang, Hung-Jen Kao
  • Publication number: 20130334982
    Abstract: Methods for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current-guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a substrate) may be provided. For some embodiments, both a current-guiding structure and second current path may be provided.
    Type: Application
    Filed: August 26, 2013
    Publication date: December 19, 2013
    Applicant: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: WEN-HUANG LIU, Chen-Fu Chu, Jiunn-Yi Chu, Chao-Chen Cheng, Hao-Chun Cheng, Feng-Hsu Fan, Yuan-Hsiao Chang
  • Publication number: 20130320358
    Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.
    Type: Application
    Filed: July 2, 2012
    Publication date: December 5, 2013
    Applicant: PHOSTEK, INC.
    Inventor: Yuan-Hsiao CHANG
  • Publication number: 20130277692
    Abstract: A semiconductor light emitting device includes a substrate and a first epitaxial structure over the substrate. The first epitaxial structure includes a first doped layer, a first light emitting layer, and a second doped layer. A first electrode is coupled to the first doped layer. A second electrode is coupled to the second doped layer facing the same direction as the first electrode. A second epitaxial structure includes a third doped layer, a second light emitting layer, and a fourth doped layer. A third electrode is coupled to the third doped layer facing the same direction as the first electrode. A fourth electrode is coupled to the fourth doped layer facing the same direction as the first electrode. An adhesive layer is between the first epitaxial structure and the second epitaxial structure.
    Type: Application
    Filed: April 19, 2012
    Publication date: October 24, 2013
    Applicant: PHOSTEK, INC.
    Inventors: Yuan-Hsiao Chang, Yi-An Lu
  • Publication number: 20130264587
    Abstract: A semiconductor light emitting device includes a substrate, a first epitaxial structure, a first substantially transparent conducting layer, a second epitaxial structure, a second substantially transparent conducting layer, and a substantially transparent insulating layer. The first epitaxial structure is over the substrate and includes a first doped layer, a first light emitting layer, and a second doped layer. The first substantially transparent conducting layer is coupled to the second doped layer. The second epitaxial structure includes a third doped layer, a second light emitting layer, and a fourth doped layer. The second substantially transparent conducting layer is coupled to the fourth doped layer. The substantially transparent insulating layer is between the first substantially transparent conducting layer and the second substantially transparent conducting layer.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Applicant: PHOSTEK, INC.
    Inventor: Yuan-Hsiao Chang