Abstract: In some embodiments, a method is provided. The method includes identifying an incident situation based upon a sensor detecting an abnormal condition. One or more life safety systems are queried to obtain life safety system data. One or more databases, comprising equipment information, chemical information, personnel information, and/or emergency response contingency procedures, are queried to obtain on-site information. The life safety system data and the on-site information are integrated together to generate incident situation information. The incident situation information is displayed through an electronic display.

Abstract: Spectral imaging systems are used to gather spectral image data on earthen material moving within an earthen material processing system, such as a mineral processing system or cement plant. Machine learning models such as 3D convolutional neural networks may be utilized to process the spectral image data to determine or classify one or more characteristics of the earthen material, such as ore grade, mineral alteration(s), moisture content, lithology and/or mineralogy. Such earthen material characteristics, or classifications thereof, may then be utilized to automatically control one or more operational characteristics of the earthen material processing system, such as rotational speed of milling equipment or flow rates of water or chemicals added to milling equipment or mineral concentration systems.

Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.

Abstract: A transistor structure includes a substrate, a source electrode, a drain electrode, a protective layer and a gate electrode. The source electrode and the drain electrode are provided on the substrate. The protective layer is provided on the substrate. The protective layer is provided between the source electrode and the drain electrode. The protective layer includes a SiNx layer and a SiOx layer. The SiOx layer is provided on the substrate, the SiNx layer is provided on the SiOx layer, and a through hole of the protective layer is formed to extend through the SiNx layer and the SiOx layer. The gate electrode is provided in the through hole, and the gate electrode is separated from at least part of the SiOx layer so as to form an air gap therebetween.

Abstract: The present disclosure provides a test system and method. The test system is configured to analyze a system platform and includes a data collector and a test monitor. The data collector is configured to receive a signal transmitted between a controller and a memory of the system platform and is configured to process the signal to generate a processed signal. The test monitor is configured to encode the processed signal into a log information, so as to determine an operation status of the system platform according to the log information.

Abstract: A photoresist includes a solvent, a polymer and an additive. The polymer is dissolved in the solvent, and the additive is dispersed in the solvent. The additive includes a double bond or includes an epoxy group. The additive has a surface tension different from a surface tension of the polymer.

Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.

Abstract: A panel device including a substrate, a conductor pad, a turning wire, and a circuit board is provided. The substrate has a first surface and a second surface connected to the first surface while a normal direction of the second surface is different from a normal direction of the first surface. The conductor pad is disposed on the first surface of the substrate. The turning wire is disposed on the substrate and extends from the first surface to the second surface. The turning wire includes a wiring layer in contact with the conductor pad and a wire covering layer covering the wiring layer. The circuit board is bonded to and electrically connected to the wire covering layer. A manufacturing method of a panel device is also provided herein.

Abstract: An integrated motor and drive assembly is disclosed and includes a housing, a motor and a drive. The housing includes a motor-accommodation portion and a drive-accommodation portion. The drive includes a power board and a control board. The power board is made of a high thermal conductivity substrate and includes a power element and an encoder disposed on the first side, the first side faces the motor, the power board and the motor are stacked along a first direction, and the second side contacts the housing to from a heat-dissipating route. The control board is disposed adjacent to the power board. The control board and the power board are arranged along a second direction perpendicular to the first direction, and the first direction is parallel to an axial direction of the motor. A part of the power board and a part of the control board are directly contacted to form an electrical connection.

Abstract: A fault analysis device and a fault analysis method of the fault analysis device are provided. A sensing circuit senses a first distorted signal on a first signal transmission path of an abnormal signal device when the abnormal signal device performs a preset operation. A signal generating circuit provides a fault test signal to a second signal transmission path of a standard device corresponding to the first signal transmission path when the standard device performs the preset operation, so as to generate a second distorted signal on the second signal transmission path, where the first distorted signal and the second distorted signal have the same signal distortion characteristics.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A cycling heat dissipation module suited for dissipating heat generated from a heat source is provided. The cycling heat dissipation module includes an evaporator, a condenser, and a micro/nano-structure. The evaporator is thermal contacted with the heat source to absorb heat generated therefrom. The condenser is connected to the evaporator to form a loop, and a working fluid is filled in the loop. The working fluid in liquid state is transformed to vapor state by absorbing heat in the evaporator, and the working fluid in vapor state is transformed to liquid state by dissipating heat in the condenser. The micro/nano-structure is disposed in the condenser to destroy a boundary layer of the working fluid while passing through the condenser.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: A resin composition includes 100 parts by weight of a fluorine-containing compound, which includes tetrafluoroethylene homopolymer, perfluoroalkoxy alkane polymer or a combination thereof; 2 parts by weight to 6 parts by weight of a butyral copolymer, which includes a unit of Formula (I), a unit of Formula (II) and a unit of Formula (III), wherein 1 is an integer of 40 to 250, m is an integer of 5 to 380, n is an integer of 55 to 2500, and wherein the butyral copolymer has a content of hydroxyl group of 21 mol % to 80 mol %; and 20 parts by weight to 150 parts by weight of an inorganic filler. The resin composition may achieve improvements in at least one of the following properties of the article made therefrom including dielectric constant, dissipation factor, X-axis coefficient of thermal expansion, weight loss percentage, tensile strength and comparative tracking index.