Abstract: A pixel structure including a scan line, a gate pattern, a first dielectric layer, a channel layer, a source, a drain, a data line, a second dielectric layer and a pixel electrode is provided. The gate pattern is electrically connected with the scan line and has an opening therein. The first dielectric layer covers the scan line and the gate pattern and it fills up the opening. Besides, the channel layer is disposed on the first dielectric layer, and the source and the drain are disposed on the channel layer. The drain is disposed above the opening of the gate pattern. The source is electrically connected with the data line, and the pixel electrode is electrically connected with the drain. The overlapping area between the gate pattern that has an opening and the drain can be kept so that the gate-drain capacitor (Cgd) is not changed.