Patents by Inventor Yuan-Hsun Wu
Yuan-Hsun Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6998226Abstract: A method of forming a patterned photoresist layer. First, an anti-reflection coating layer is formed on a substrate. Next, a first bake is performed. A photoresist layer is then formed on the anti-reflection coating layer. Exposure is performed. A second bake is performed, wherein the temperature difference between the first bake and the second bake is about 35 ° C.˜55 ° C. Finally, development is performed. The patterned photoresist layer features have perfect profiles in accordance with this invention.Type: GrantFiled: July 10, 2002Date of Patent: February 14, 2006Assignee: Nanya Technology CorporationInventors: Yuan-Hsun Wu, Wen-Bin Wu, Yung Long Hung, Ya Chih Wang
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Patent number: 6977715Abstract: A method for optimizing NILS of exposed lines includes providing a photomask layout which has a first straight line and a second straight line parallel with the first straight line and is applied to a Quasar 90 illumination, and adding a first assist pattern between the first and second straight lines, wherein the first assist pattern has a plurality of geometric patterns with similar size arranging as a line parallel with the first straight line.Type: GrantFiled: May 19, 2004Date of Patent: December 20, 2005Assignee: Nanya Technology Corp.Inventor: Yuan-Hsun Wu
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Publication number: 20050259237Abstract: A method for optimizing NILS of exposed lines includes providing a photomask layout which has a first straight line and a second straight line parallel with the first straight line and is applied to a Quasar 90 illumination, and adding a first assist pattern between the first and second straight lines, wherein the first assist pattern has a plurality of geometric patterns with similar size arranging as a line parallel with the first straight line.Type: ApplicationFiled: May 19, 2004Publication date: November 24, 2005Inventor: Yuan-Hsun WU
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Publication number: 20050243440Abstract: An aperture plate for lithography systems capable of improving NILS. The aperture plate includes a light-intercepting region and a light-transmitting region. The light-intercepting region has a reference center point. A horizontal reference line and a vertical reference line are defined on the light-intercepting region and intersect the reference center point. The light-transmitting region includes four pole apertures defining a central area. Two of the pole apertures are positioned on the horizontal reference line, and the other pole apertures are positioned on the vertical reference line. The light-transmitting region further includes at least a symmetric pattern aperture positioned in the central area, wherein the symmetric pattern aperture has a symmetric center overlapping the reference center point.Type: ApplicationFiled: April 28, 2004Publication date: November 3, 2005Inventor: Yuan-Hsun WU
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Publication number: 20050229147Abstract: An H-shaped test key layout for exclusively monitoring 3-foil lens aberration effects during the fabrication of deep-trench capacitor memory devices is disclosed. The COMA lens aberration effect that used to occur along with the 3-foil lens aberration effect is now eliminated by this test key layout.Type: ApplicationFiled: April 12, 2004Publication date: October 13, 2005Inventor: Yuan-Hsun WU
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Publication number: 20050221560Abstract: A method of forming a vertical memory device with a rectangular trench. First, a substrate covered by a photoresist layer is provided. Next, the photoresist layer is defined by a mask to form a rectangular opening, wherein the mask has two rectangular transparent patterns arranged with a predetermined interval. Next, the substrate is etched using the defined photoresist layer as a mask to form a single rectangular trench and the photoresist layer is then removed. Finally, a trench capacitor and a vertical transistor are successively formed in the rectangular trench to finish the vertical memory device.Type: ApplicationFiled: May 27, 2005Publication date: October 6, 2005Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Yu-Sheng Shu, Yuan-Hsun Wu, Chung-Yuan Lee, Shian-Jyh Lin
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Publication number: 20050214651Abstract: A pupil aperture plate situated on a light path of an optical lithography system for providing specific illumination patterns is disclosed. The pupil aperture plate includes a plate body having thereon a pole aperture (defined by ?inner) located at the center of the plate. A set of four sector apertures, each of which has an opening angle ?, radiating from a reference center point of the pole aperture. The distance of the sector aperture from the reference center point of the pole aperture is defined by ?outer. The pupil aperture plate provides Bow-Pole and Quasar illumination patterns in combination with conventional and annular illuminations, respectively.Type: ApplicationFiled: March 25, 2004Publication date: September 29, 2005Inventor: Yuan-Hsun WU
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Patent number: 6929902Abstract: A method of preventing repeated collapse in a reworked photoresist layer. First, oxygen-containing plasma is applied to remove a collapsed photoresist. Because the plasma containing oxygen reacts with a bottom anti-reflect layer comprising SiOxNy, some acids are produced on the bottom anti-reflect layer, resulting in undercutting in a subsequently reworked photoresist. Next, an alkaline solution treatment is performed on the anti-reflect layer after the collapsed photoresist layer is removed. Finally, the reworked photoresist with is formed on the anti-reflect layer, without undercutting.Type: GrantFiled: February 20, 2003Date of Patent: August 16, 2005Assignee: Nanya Technology CorporationInventors: Yuan-Hsun Wu, Teng-Yen Huang, Wen-Bin Wu, Yi-Nan Chen
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Publication number: 20050100827Abstract: A photolithography method for reducing effects of lens aberration. A photolithography apparatus is provided with a first reticle therein, having at least one first rectangular pattern thereon, a first photolithography is performed on a wafer by the photolithography apparatus to transfer the first rectangular pattern thereonto by simultaneously moving the first reticle and the wafer in a direction parallel to the short sides of the first rectangular pattern. The first reticle is replaced with a second reticle having at least one second rectangular pattern thereon and a second photolithography is performed by the photolithography apparatus to transfer the second rectangular pattern onto the wafer by simultaneously moving the second reticle and the wafer in a 90° plus or minus rotation in a direction parallel to the short sides of the second rectangular pattern.Type: ApplicationFiled: August 13, 2003Publication date: May 12, 2005Inventors: Chun-Cheng Liao, Yuan-Hsun Wu
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Patent number: 6866975Abstract: A best focus determining method. First, a test mask is provided, wherein the test mask comprises a transparent substrate and an opaque layer covering parts of the transparent substrate to define a first transparent area with 0° phase and a second transparent area with 90° phase. The sizes of the two transparent areas are the same. Next, a light source is provided and transmits the test mask to perform an exposure. Then, a first image corresponding to the first transparent area and a second image corresponding to the second transparent area are formed. The sizes of the first and second images are measured to ensure the best focus possible.Type: GrantFiled: December 5, 2002Date of Patent: March 15, 2005Assignee: Nanya Technology CorporationInventor: Yuan-Hsun Wu
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Patent number: 6858355Abstract: A mask for defining a guard ring pattern. The mask includes a transparent substrate, a light-shielding layer, and at least one pair of assisted line patterns. The light-shielding layer is disposed on the transparent substrate and has a rectangular ring pattern composed of a plurality of opening patterns to define the guard ring pattern. The pair of assisted line patterns is parallelized by a predetermined interval on both sides of at least one section of the rectangular ring and have a predetermined width. Moreover, a method for defining a guard ring pattern is disclosed. First, a semiconductor substrate covered by an energy sensitive layer is provided. Next, photolithography is performed on the energy sensitive layer using the mask to transfer the guard ring pattern inside.Type: GrantFiled: December 13, 2002Date of Patent: February 22, 2005Assignee: Nanya Technology CorporationInventors: Hsien-Jung Wang, Yuan-Hsun Wu
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Patent number: 6847445Abstract: The present invention provides a method for estimating repair accuracy of a mask shop. The method comprises the steps of providing a mask having a light-shielding layer with a pattern of a plurality of lines, each of which has a defect, using the mask shop to repair the defects. Contaminated areas are formed in the vicinity of areas where the defects are repaired, measuring first light intensities of the contaminated areas, and second and third light intensities of two sides of the contaminated areas, and calculating ratios of means of the second and third light intensities to the first light intensities to estimate the repair accuracy.Type: GrantFiled: November 6, 2001Date of Patent: January 25, 2005Assignee: Nanya Technology CorporationInventor: Yuan-Hsun Wu
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Publication number: 20040219438Abstract: A photomask structure for reducing lens aberration and pattern displacement and method thereof. The photomask consists of a transparent substrate and a light-shielding layer, with the light-shielding layer including an array pattern area and a plurality of assist patterns disposed therein. The distance between the assist pattern and its upper and lower array patterns is equal, and the length of the assist pattern is equal to the width of the array pattern. The method of reducing lens aberration and pattern displacement includes providing a substrate covered by a photoresist layer, forming patterns on the photoresist layer by a photomask, and etching an array trench area in the substrate using a patterned photoresist as a mask. According to the present invention, the uniformity of critical dimension between array patterns is improved and pattern displacement is reduced significantly.Type: ApplicationFiled: September 8, 2003Publication date: November 4, 2004Applicant: Nanya Technology CorporationInventor: Yuan-Hsun Wu
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Publication number: 20040202964Abstract: A method for enhancing adhesion between a reworked photoresist and an underlying oxynitride film. A photoresist pattern layer is formed on an oxynitride layer overlying a substrate. The photoresist pattern layer is removed by acidic solution or oxygen-containing plasma. A surface treatment is performed on the oxynitride layer using a development solution to repair the damaged oxynitride layer due to removing the overlying photoresist pattern layer. A reworked photoresist pattern layer is formed on the oxynitride layer.Type: ApplicationFiled: July 1, 2003Publication date: October 14, 2004Applicant: Nanya Technology CorporationInventors: Wen-Bin Wu, Yuan-Hsun Wu, Yi-Nan Chen, Teng-Yen Huang
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Patent number: 6759328Abstract: A mask and method for contact hole exposure. First, a mask including a transparent substrate, a phase shift layer installed on the transparent substrate to define a series of patterns having contact hole areas set in array, an a plurality of metal lines installed on the phase shift layer between the adjacent contact hole areas is provided. Then, an exposure is performed by transmitting a light source, such as deep ultraviolet (UV), extreme ultraviolet, or X-ray, through the mask after the metal lines absorb high degree diffraction waves.Type: GrantFiled: July 18, 2002Date of Patent: July 6, 2004Assignee: Nanya Technology CorporationInventor: Yuan-Hsun Wu
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Publication number: 20040081923Abstract: A method of preventing repeated collapse in a reworked photoresist layer. First, oxygen-containing plasma is applied to remove a collapsed photoresist. Because the plasma containing oxygen reacts with a bottom anti-reflect layer comprising SiOxNy, some acids are produced on the bottom anti-reflect layer, resulting in undercutting in a subsequently reworked photoresist. Next, an alkaline solution treatment is performed on the anti-reflect layer after the collapsed photoresist layer is removed. Finally, the reworked photoresist with is formed on the anti-reflect layer, without undercutting.Type: ApplicationFiled: February 20, 2003Publication date: April 29, 2004Applicant: Nanya Technology CorporationInventors: Yuan-Hsun Wu, Teng-Yen Huang, Wen-Bin Wu, Yi-Nan Chen
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Publication number: 20040079729Abstract: A process for etching a metal layer. First, a semiconducting substrate having a metal layer and an anti-reflective layer thereon is provided. Next, the surface of the anti-reflective layer is treated with a weak base aqueous solution. Next, a photoresist layer is formed on the treated anti-reflective layer and then patterned. Next, the treated anti-reflective layer and metal layer are etched using the photoresist pattern as a mask. Finally, the photoresist pattern and anti-reflective layer are removed. The present invention prevents undercut and collapse of photoresist pattern, thus obtaining an accurate metal layer pattern.Type: ApplicationFiled: February 27, 2003Publication date: April 29, 2004Applicant: Nanya Technology CorporationInventors: Yi-Nan Chen, Wen-Bin Wu, Teng-Yen Huang, Chun-Cheng Liao, Yuan-Hsun Wu, Hung Wen Lin
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Publication number: 20040076893Abstract: A method of forming a vertical memory device with a rectangular trench. First, a substrate covered by a photoresist layer is provided. Next, the photoresist layer is defined by a mask to form a rectangular opening, wherein the mask has two rectangular transparent patterns arranged with a predetermined interval. Next, the substrate is etched using the defined photoresist layer as a mask to form a single rectangular trench and the photoresist layer is then removed. Finally, a trench capacitor and a vertical transistor are successively formed in the rectangular trench to finish the vertical memory device.Type: ApplicationFiled: May 29, 2003Publication date: April 22, 2004Applicant: Nanya Technology CorporationInventors: Yu-Sheng Shu, Yuan-Hsun Wu, Chung-Yuan Lee, Shian-Jyh Lin
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Publication number: 20040053142Abstract: A mask for defining a guard ring pattern. The mask includes a transparent substrate, a light-shielding layer, and at least one pair of assisted line patterns. The light-shielding layer is disposed on the transparent substrate and has a rectangular ring pattern composed of a plurality of opening patterns to define the guard ring pattern. The pair of assisted line patterns is parallelized by a predetermined interval on both sides of at least one section of the rectangular ring and have a predetermined width. Moreover, a method for defining a guard ring pattern is disclosed. First, a semiconductor substrate covered by an energy sensitive layer is provided. Next, photolithography is performed on the energy sensitive layer using the mask to transfer the guard ring pattern inside.Type: ApplicationFiled: December 13, 2002Publication date: March 18, 2004Applicant: Nanya Technology CorporationInventors: Hsien-Jung Wang, Yuan-Hsun Wu
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Patent number: 6699800Abstract: An assist pattern design method for lithography C/H process that includes the following steps: determining the exposure wavelength of a lithography machine light source; determining a minimum resolution line width by the sigma, process integration parameter and numerical aperture of the lithography machine; recovering the minimum line width on a mask according to the miniature scale of the determined minimum resolution line width; and using a line pattern smaller than the recovered minimum line width to connect multiply C/H patterns on the mask.Type: GrantFiled: March 28, 2002Date of Patent: March 2, 2004Assignee: Nanya Technology CorporationInventor: Yuan-Hsun Wu