Patents by Inventor Yuan-Hung Liu

Yuan-Hung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120679
    Abstract: A bracket and a terminal equipment are provided. The bracket is provided for a terminal device to be installed thereon and includes a bracket body, two installing elements, and at least one holding element. The two installing elements respectively protrude outward from two sides of the bracket body, and each of the two installing elements includes an engaging portion. The two installing elements are configured to be inserted into the terminal device so the terminal device is installed on the bracket, and each of the engaging portions is configured such that each of the installing elements is engaged with and retained in the terminal device. The holding element protrudes outward from the bracket body and is configured to be inserted into a loading hole of the terminal device.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 11, 2024
    Inventors: Yuan-Yu CHEN, Ming-Hung HUNG, Ying Chih LIU
  • Publication number: 20240105775
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first source/drain structure and a second source/drain structure over and in a substrate. The method includes forming a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack over the substrate. Each of the first gate stack or the second gate stack is wider than each of the third gate stack or the fourth gate stack. The method includes forming a first contact structure and a second contact structure over the first source/drain structure and the second source/drain structure respectively. A first average width of the first contact structure is substantially equal to a second average width of the second contact structure.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu CHIANG, Hsiao-Han LIU, Yuan-Hung TSENG, Chih-Yung LIN
  • Patent number: 10269848
    Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Kai Liao, Han-Chi Liu, Yuan-Hung Liu, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 10153338
    Abstract: A method of forming a device includes forming a through via extending into a substrate. The method further includes forming a first insulating layer over the surface of the substrate. The method further includes forming a first metallization layer in the first insulating layer and electrically connected to the through via. The method further includes forming a capacitor over the first metallization layer, wherein the capacitor comprises a first capacitor dielectric layer and a second capacitor dielectric layer. The method further includes depositing a continuous second insulating layer over the first insulating layer. The capacitor is within the second insulating layer. The method further includes depositing a third insulating layer over the second insulating layer. The method further includes forming a second metallization layer in the third insulating layer. A bottom surface of the second metallization layer is below a bottom surface of the third insulating layer.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hua Chang, Der-Chyang Yeh, Kuang-Wei Cheng, Yuan-Hung Liu, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 9953920
    Abstract: An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first photo-sensitive dielectric layer formed over the interlayer dielectric layer, wherein the first photo-sensitive dielectric layer comprises a first metal structure and a second photo-sensitive dielectric layer formed over the first photo-sensitive dielectric, wherein the second photo-sensitive dielectric layer comprises a second metal structure having a bottom surface coplanar with a top surface of the first metal structure.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yu Chen, Ku-Feng Yang, Tasi-Jung Wu, Lin-Chih Huang, Yuan-Hung Liu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 9773701
    Abstract: A method of forming an integrated circuit includes forming at least one opening through a first surface of a substrate. The method further includes forming at least one conductive structure in the at least one opening. The method further includes removing a portion of the substrate to form a processed substrate having the first surface and a second surface opposite the first surface and to expose a portion of the at least one conductive structure adjacent to the second surface. The at least one conductive structure continuously extending from the first surface through the processed substrate to the second surface of the processed substrate, at least one sidewall of the at least one conductive structure spaced from a sidewall of the at least one opening by an air gap.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: September 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Hung Liu, Ku-Feng Yang, Pei-Ching Kuo, Ming-Tsu Chung, Hsin-Yu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20170236863
    Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Inventors: Yin-Kai Liao, Han-Chi Liu, Yuan-Hung Liu, Dun-Nian Yaung, Jen-Cheng Liu
  • Publication number: 20170229534
    Abstract: A method of forming a device includes forming a through via extending into a substrate. The method further includes forming a first insulating layer over the surface of the substrate. The method further includes forming a first metallization layer in the first insulating layer and electrically connected to the through via. The method further includes forming a capacitor over the first metallization layer, wherein the capacitor comprises a first capacitor dielectric layer and a second capacitor dielectric layer. The method further includes depositing a continuous second insulating layer over the first insulating layer. The capacitor is within the second insulating layer. The method further includes depositing a third insulating layer over the second insulating layer. The method further includes forming a second metallization layer in the third insulating layer. A bottom surface of the second metallization layer is below a bottom surface of the third insulating layer.
    Type: Application
    Filed: April 26, 2017
    Publication date: August 10, 2017
    Inventors: Chun Hua CHANG, Der-Chyang YEH, Kuang-Wei CHENG, Yuan-Hung LIU, Shang-Yun HOU, Wen-Chih CHIOU, Shin-Puu JENG
  • Patent number: 9660016
    Abstract: A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hua Chang, Der-Chyang Yeh, Kuang-Wei Cheng, Yuan-Hung Liu, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 9640582
    Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: May 2, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Kai Liao, Han-Chi Liu, Yuan-Hung Liu, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 9418999
    Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ta Wu, Jason Lee, Chung Chien Wang, Hsing-Lien Lin, Yu-Jen Wang, Yeur-Luen Tu, Chern-Yow Hsu, Yuan-Hung Liu, Chi-Hsin Lo, Chia-Shiung Tsai
  • Publication number: 20160049495
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.
    Type: Application
    Filed: August 18, 2014
    Publication date: February 18, 2016
    Applicants: LAM RESEARCH CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kristina TREVINO, Yuan-Hung LIU, Gabriel Padron WELLS, Xing ZHANG, Hoong Shing WONG, Chang Ho MAENG, Taejoon HAN, Gowri KAMARTHY, Isabelle ORAIN, Ganesh UPADHYAYA
  • Patent number: 9263382
    Abstract: A structure includes a substrate, and an interconnect structure over the substrate. The structure further includes a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer. The structure further includes a dielectric layer having a first portion over the interconnect structure and a second portion within the TSV, wherein the first portion and the second portion comprise a same material. The conductive material layer includes a first section separated from substrate by the second portion of the dielectric layer. The conductive material layer further includes a second section over a top surface of the second portion of the dielectric layer. The conductive material layer further includes a third section over the second section, wherein the third section has a width greater than a width of the second section.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: February 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ku-Feng Yang, Tsang-Jiuh Wu, Yi-Hsiu Chen, Ebin Liao, Yuan-Hung Liu, Wen-Chih Chiou
  • Patent number: 9252238
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: February 2, 2016
    Assignees: LAM RESEARCH CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kristina Trevino, Yuan-Hung Liu, Gabriel Padron Wells, Xing Zhang, Hoong Shing Wong, Chang Ho Maeng, Taejoon Han, Gowri Kamarthy, Isabelle Orain, Ganesh Upadhyaya
  • Publication number: 20150279886
    Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.
    Type: Application
    Filed: May 26, 2015
    Publication date: October 1, 2015
    Inventors: Yin-Kai Liao, Han-Chi Liu, Yuan-Hung Liu, Dun-Nian Yaung, Jen-Cheng Liu
  • Publication number: 20150235940
    Abstract: An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first photo-sensitive dielectric layer formed over the interlayer dielectric layer, wherein the first photo-sensitive dielectric layer comprises a first metal structure and a second photo-sensitive dielectric layer formed over the first photo-sensitive dielectric, wherein the second photo-sensitive dielectric layer comprises a second metal structure having a bottom surface coplanar with a top surface of the first metal structure.
    Type: Application
    Filed: April 13, 2015
    Publication date: August 20, 2015
    Inventors: Hsin-Yu Chen, Ku-Feng Yang, Tasi-Jung Wu, Lin-Chih Huang, Yuan-Hung Liu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20150228541
    Abstract: A method of forming an integrated circuit includes forming at least one opening through a first surface of a substrate. The method further includes forming at least one conductive structure in the at least one opening. The method further includes removing a portion of the substrate to form a processed substrate having the first surface and a second surface opposite the first surface and to expose a portion of the at least one conductive structure adjacent to the second surface. The at least one conductive structure continuously extending from the first surface through the processed substrate to the second surface of the processed substrate, at least one sidewall of the at least one conductive structure spaced from a sidewall of the at least one opening by an air gap.
    Type: Application
    Filed: April 22, 2015
    Publication date: August 13, 2015
    Inventors: Yuan-Hung LIU, Ku-Feng YANG, Pei-Ching KUO, Ming-Tsu CHUNG, Hsin-Yu CHEN, Tsang-Jiuh WU, Wen-Chih CHIOU
  • Patent number: 9059262
    Abstract: An integrated circuit includes a substrate having a first surface and a second surface. At least one conductive structure continuously extends through the substrate. At least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: June 16, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Hung Liu, Ku-Feng Yang, Pei-Ching Kuo, Ming-Tsu Chung, Hsin-Yu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 9041841
    Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Kai Liao, Han-Chi Liu, Yuan-Hung Liu, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 9006101
    Abstract: An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanar with a top surface of the first metal line.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yu Chen, Ku-Feng Yang, Tasi-Jung Wu, Lin-Chih Huang, Yuan-Hung Liu, Tsang-Jiuh Wu, Wen-Chih Chiou