Patents by Inventor Yuan-Hung Liu
Yuan-Hung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150041874Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Inventors: Chih-Ta Wu, Jason Lee, Chung Chien Wang, Hsing-Lien Lin, Yu-Jen Wang, Yeur-Luen Tu, Chern-Yow Hsu, Yuan-Hung Liu, Chi-Hsin Lo, Chia-Shiung Tsai
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Publication number: 20150037960Abstract: A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor.Type: ApplicationFiled: October 15, 2014Publication date: February 5, 2015Inventors: Chun Hua CHANG, Der-Chyang YEH, Kuang-Wei CHENG, Yuan-Hung LIU, Shang-Yun HOU, Wen-Chih CHIOU, Shin-Puu JENG
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Publication number: 20150024584Abstract: Methods for fabricating integrated circuits with reduced replacement metal gate height variability are provided. In an embodiment, a method includes providing a semiconductor substrate with a fin supported thereon and forming a conformal material layer overlying the fin and the semiconductor substrate. A trench is etched within the conformal material layer such that the trench exposes a surface of the fin and the semiconductor substrate. A conductive gate structure is formed within the trench, the conformal material layer is removed, and spacers are formed on the sidewalls of the conductive gate.Type: ApplicationFiled: July 17, 2013Publication date: January 22, 2015Inventors: Gabriel Padron Wells, Yuan-Hung Liu, Kristina Trevino, Chang Ho Maeng, Taejoon Han
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Patent number: 8889507Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.Type: GrantFiled: June 20, 2007Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Ta Wu, Jason Lee, Chung Chien Wang, Hsing-Lien Lin, Yu-Jen Wang, Yeur-Luen Tu, Chern-Yow Hsu, Yuan-Hung Liu, Chi-Hsin Lo, Chia-Shiung Tsai, Lucy Chang, Chia-Lin Chen, Ming-Chih Tsai
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Publication number: 20140327151Abstract: A structure includes a substrate, and an interconnect structure over the substrate. The structure further includes a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer. The structure further includes a dielectric layer having a first portion over the interconnect structure and a second portion within the TSV, wherein the first portion and the second portion comprise a same material. The conductive material layer includes a first section separated from substrate by the second portion of the dielectric layer. The conductive material layer further includes a second section over a top surface of the second portion of the dielectric layer. The conductive material layer further includes a third section over the second section, wherein the third section has a width greater than a width of the second section.Type: ApplicationFiled: July 17, 2014Publication date: November 6, 2014Inventors: Ku-Feng YANG, Tsang-Jiuh WU, Yi-Hsiu CHEN, Ebin LIAO, Yuan-Hung LIU, Wen-Chih CHIOU
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Patent number: 8878338Abstract: Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers.Type: GrantFiled: May 31, 2012Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hua Chang, Der-Chyang Yeh, Kuang-Wei Cheng, Yuan-Hung Liu, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng
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Patent number: 8803322Abstract: The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill.Type: GrantFiled: October 13, 2011Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ku-Feng Yang, Tsang-Jiuh Wu, Yi-Hsiu Chen, Ebin Liao, Yuan-Hung Liu, Wen-Chih Chiou
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Publication number: 20140061924Abstract: An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanr with a top surface of the first metal line.Type: ApplicationFiled: August 31, 2012Publication date: March 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yu Chen, Ku-Feng Yang, Tasi-Jung Wu, Lin-Chih Huang, Yuan-Hung Liu, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20130320493Abstract: Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hua CHANG, Der-Chyang YEH, Kuang-Wei CHENG, Yuan-Hung LIU, Shang-Yun HOU, Wen-Chih CHIOU, Shin-Puu JENG
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Patent number: 8546235Abstract: An integrated circuit includes a substrate and a first metal-insulator-metal (MIM) capacitor disposed over the substrate. The MIM capacitor includes a first metallic capacitor plate disposed over the substrate. At least one first insulator layer is disposed over the first metallic capacitor plate. A second metallic capacitor plate is disposed over the at least one first insulator layer. At least one first dielectric layer is disposed over the substrate. At least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer.Type: GrantFiled: May 5, 2011Date of Patent: October 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Hui Huang, Yuan-Hung Liu, Ming-Fa Chen
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Patent number: 8440540Abstract: A method includes forming a protective layer with an opening over a substrate, thereafter implanting a dopant into a substrate region through the opening, the protective layer protecting a different substrate region, and reducing thickness of the protective layer. A different aspect includes etching a substrate to form a recess therein, thereafter implanting a dopant into a substrate region within the recess and through an opening in a protective layer provided over the substrate, and reducing thickness of the protective layer. Another aspect includes forming a protective layer over a substrate, forming photoresist having an opening over the protective layer, etching the protective layer through the opening to expose the substrate, etching the substrate to form a recess in the substrate, implanting a dopant into a substrate portion, the protective layer protecting a different substrate portion thereunder, and etching the protective layer to reduce its thickness.Type: GrantFiled: October 2, 2009Date of Patent: May 14, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Chi Liu, Dun-Nian Yaung, Jen-Cheng Liu, Yuan-Hung Liu
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Publication number: 20130093098Abstract: The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ku-Feng YANG, Tsang-Jiuh WU, Yi-Hsiu CHEN, Ebin LIAO, Yuan-Hung LIU, Wen-Chih CHIOU
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Publication number: 20120280358Abstract: An integrated circuit includes a substrate and a first metal-insulator-metal (MIM) capacitor disposed over the substrate. The MIM capacitor includes a first metallic capacitor plate disposed over the substrate. At least one first insulator layer is disposed over the first metallic capacitor plate. A second metallic capacitor plate is disposed over the at least one first insulator layer. At least one first dielectric layer is disposed over the substrate. At least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer.Type: ApplicationFiled: May 5, 2011Publication date: November 8, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sung-Hui HUANG, Yuan-Hung LIU, Ming-Fa CHEN
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Publication number: 20120217611Abstract: An integrated circuit includes a substrate having a first surface and a second surface. At least one conductive structure continuously extends through the substrate. At least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap.Type: ApplicationFiled: February 24, 2011Publication date: August 30, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Hung LIU, Ku-Feng YANG, Pei-Ching KUO, Ming-Tsu CHUNG, Hsin-Yu CHEN, Tsang-Jiuh WU, Wen-Chih CHIOU
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Publication number: 20110081766Abstract: A method includes forming a protective layer with an opening over a substrate, thereafter implanting a dopant into a substrate region through the opening, the protective layer protecting a different substrate region, and reducing thickness of the protective layer. A different aspect includes etching a substrate to form a recess therein, thereafter implanting a dopant into a substrate region within the recess and through an opening in a protective layer provided over the substrate, and reducing thickness of the protective layer. Another aspect includes forming a protective layer over a substrate, forming photoresist having an opening over the protective layer, etching the protective layer through the opening to expose the substrate, etching the substrate to form a recess in the substrate, implanting a dopant into a substrate portion, the protective layer protecting a different substrate portion thereunder, and etching the protective layer to reduce its thickness.Type: ApplicationFiled: October 2, 2009Publication date: April 7, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chi Liu, Dun-Nian Yaung, Jen-Cheng Liu, Yuan-Hung Liu
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Patent number: 7883917Abstract: A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern.Type: GrantFiled: January 15, 2009Date of Patent: February 8, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Chyi Liu, Yuan-Hung Liu, Gwo-Yuh Shiau, Yuan-Chih Hsieh, Chi-Hsin Lo, Chia-Shiung Tsai
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Patent number: 7824998Abstract: A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor.Type: GrantFiled: January 22, 2009Date of Patent: November 2, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yuan-Hung Liu, Ming Chyi Liu, Yeur-Luen Tu, Chi-Hsin Lo, Chia-Shiung Tsai
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Publication number: 20100091163Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.Type: ApplicationFiled: September 10, 2009Publication date: April 15, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yin-Kai Liao, Han-Chi Liu, Yuan-Hung Liu, Dun-Nian Yaung, Jen-Cheng Liu
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Patent number: 7586145Abstract: An EEPROM flash memory device having a floating gate electrode enabling a reduced erase voltage and method for forming the same, the floating gate electrode including an outer edge portion including multiple charge transfer pointed tips.Type: GrantFiled: July 27, 2005Date of Patent: September 8, 2009Assignee: Taiwan Semiconductor Manufacturing Co. LtdInventors: Yuan-Hung Liu, Shih-Chi Fu, Chi-Hsin Lo, Chia-Shiung Tsai
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Patent number: 7563675Abstract: A method is disclosed for etching a polysilicon material in a manner that prevents formation of an abnormal polysilicon profile. The method includes providing a substrate with a word line and depositing a polysilicon layer over said substrate and word line. An organic bottom antireflective coating (BARC) layer is then deposited over said polysilicon layer. A ladder etch is performed to remove the BARC layer and a portion of the polysilicon layer. The ladder etch consists of a series of etch cycles, with each cycle including a breakthrough etch and a soft landing etch. The breakthrough and soft landing etches are performed using different etchant gases, and at different source and bias powers, pressures, gas flow rates, and periods of time. The ladder etch results in a smooth polysilicon surface without abrupt steps.Type: GrantFiled: July 24, 2007Date of Patent: July 21, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chang Liu, Yuan-Hung Liu, Chia-Shiung Tsai