Abstract: The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

Abstract: The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

Abstract: The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

Abstract: The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

Abstract: The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

Abstract: The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

Abstract: The present disclosure provides a method forming a field effect transistor (FET) in accordance with some embodiments. The method includes performing an etching process to a semiconductor substrate, thereby forming recesses in source and drain (S/D) regions of the semiconductor substrate; forming a passivation material layer of a first semiconductor in the recesses; and epitaxially growing a second semiconductor material, thereby forming S/D features in the recesses, wherein the S/D features are separated from the semiconductor substrate by the passivation material layer.

Abstract: A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed from the top, in a round shape or a polygon shape having an angle between adjacent edges greater than 90°. Therefore, the step coverage of the later formed metal layer can be improved.

Abstract: A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed from the top, in a round shape or a polygon shape having an angle between adjacent edges greater than 90°. Therefore, the step coverage of the later formed metal layer can be improved.

Abstract: A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed from the top, in a round shape or a polygon shape having an angle between adjacent edges greater than 90°. Therefore, the step coverage of the later formed metal layer can be improved.

Abstract: The present disclosure provides a method forming a field effect transistor (FET) in accordance with some embodiments. The method includes performing an etching process to a semiconductor substrate, thereby forming recesses in source and drain (S/D) regions of the semiconductor substrate; forming a passivation material layer of a first semiconductor in the recesses; and epitaxially growing a second semiconductor material, thereby forming S/D features in the recesses, wherein the S/D features are separated from the semiconductor substrate by the passivation material layer.

Abstract: A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed from the top, in a round shape or a polygon shape having an angle between adjacent edges greater than 90°. Therefore, the step coverage of the later formed metal layer can be improved.

Abstract: A new method is provided to create a polysilicon fuse. The invention provides for applying a first oxide plasma treatment to the surface of the created polysilicon fuse, creating a thin layer of native oxide over the surface of the created polysilicon fuse, followed by a DI water rinse. This thin layer of native oxide is made more robust by applying a second oxide plasma treatment to exposed surfaces, this more robust layer of native oxide protects the polysilicon fuse during subsequent processing steps of wet photoresist and polymer removal.

Abstract: A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous silicon layer is resistant to attack during the post-etch solvent stripping operation due to the oxidation of exposed portions of the amorphous silicon layer by use of an oxygen plasma.

Abstract: The present subject matter relates to a method of stripping a photoresist after the photoresist film has been subjected to a high dose and high energy ion implant process. The method involves soaking the photoresist film in DI water, dry etching with oxygen plasma, and immersing in Caro's acid solution to improve the throughput of removing the film from the underlying substrate. The method can also be used to strip photoresist that has been hardened or altered by other types of processes such as dry etch transfer steps and chemical treatments. In some applications, the dry etching step may be omitted from the stripping process or the dry etching step may be combined with the water soak in an integrated process.

Abstract: A new method is provided to create a polysilicon fuse. The invention provides for applying a first oxide plasma treatment to the surface of the created polysilicon fuse, creating a thin layer of native oxide over the surface of the created polysilicon fuse, followed by a DI water rinse. This thin layer of native oxide is made more robust by applying a second oxide plasma treatment to exposed surfaces, this more robust layer of native oxide protects the polysilicon fuse during subsequent processing steps of wet photoresist and polymer removal.

Abstract: A new method is provided to create a polysilicon fuse. The invention provides for applying a first oxide plasma treatment to the surface of the created polysilicon fuse, creating a thin layer of native oxide over the surface of the created polysilicon fuse, followed by a DI water rinse. This thin layer of native oxide is made more robust by applying a second oxide plasma treatment to exposed surfaces, this more robust layer of native oxide protects the polysilicon fuse during subsequent processing steps of wet photoresist and polymer removal.

Abstract: A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous silicon layer is resistant to attack during the post-etch solvent stripping operation due to the oxidation of exposed portions of the amorphous silicon layer by use of an oxygen plasma.

Abstract: The present subject matter relates to a method of stripping a photoresist after the photoresist film has been subjected to a high dose and high energy ion implant process. The method involves soaking the photoresist film in DI water, dry etching with oxygen plasma, and immersing in Caro's acid solution to improve the throughput of removing the film from the underlying substrate. The method can also be used to strip photoresist that has been hardened or altered by other types of processes such as dry etch transfer steps and chemical treatments. In some applications, the dry etching step may be omitted from the stripping process or the dry etching step may be combined with the water soak in an integrated process.

Abstract: A method of forming very small silicon nitride spacers in split-gate flash EPROMs is disclosed which prevent the occurrence of “write disturb”, unwanted reverse tunneling, or erasing. This is accomplished by forming spacers with well-controlled dimensions and well-defined shapes through a judicious use of a fully wet etch technique, including main-etch and over-etch. The use of a phosphoric acid solution in combination with sulfuric acid+hydrogen peroxide widens the process window from a few seconds to several minutes so that the small-dimensioned silicon nitride spacers can be better controlled than it has been possible in the past. In the first embodiment phosphoric solution is used both for main-etch and for over-etch. In the second embodiment, phosphoric solution is used for main-etch only, while the sulfuric+hydrogen peroxide solution is used as an over-etch in forming the tiny silicon nitride spacers of the invention.

Abstract: A device is described for accurately transferring multiple individual fluids from multiple source containers into a single receiving container. Fluid flows from the multiple source containers through individual fluid conduits to a chamber having a single fluid outlet conduit. The fluid outlet conduit is in fluid communication with a single receiving container. A pressure conduit is in communication with the chamber for alternately creating positive and negative pressures in the chamber to cause fluid to flow from the individual source containers into the chamber, and to cause fluid to flow from the chamber into the receiving container in response to commands from a control means in the device.