Abstract: A new method is provided to create a polysilicon fuse. The invention provides for applying a first oxide plasma treatment to the surface of the created polysilicon fuse, creating a thin layer of native oxide over the surface of the created polysilicon fuse, followed by a DI water rinse. This thin layer of native oxide is made more robust by applying a second oxide plasma treatment to exposed surfaces, this more robust layer of native oxide protects the polysilicon fuse during subsequent processing steps of wet photoresist and polymer removal.

Abstract: A method of forming very small silicon nitride spacers in split-gate flash EPROMs is disclosed which prevent the occurrence of “write disturb”, unwanted reverse tunneling, or erasing. This is accomplished by forming spacers with well-controlled dimensions and well-defined shapes through a judicious use of a fully wet etch technique, including main-etch and over-etch. The use of a phosphoric acid solution in combination with sulfuric acid+hydrogen peroxide widens the process window from a few seconds to several minutes so that the small-dimensioned silicon nitride spacers can be better controlled than it has been possible in the past. In the first embodiment phosphoric solution is used both for main-etch and for over-etch. In the second embodiment, phosphoric solution is used for main-etch only, while the sulfuric+hydrogen peroxide solution is used as an over-etch in forming the tiny silicon nitride spacers of the invention.

Abstract: A method for in-situ descum/hot bake/dry etch a polyimide photoresist layer and a passivation layer in a singe process chamber is disclosed. A process chamber that can be used for conducting in-situ a descum, a hot bake and a dry etch process sequentially in the same chamber is also disclosed. In the method, a process chamber equipped with a wafer platform and a wafer backside heating and cooling device is first provided, followed by the step of positioning a wafer that has a passivation layer and a patterned polyimide photoresist layer on top of the platform. An oxygen plasma is then generated in the chamber cavity to conduct a descum process, followed by flowing a heated inert gas onto a backside of the wafer to conduct a hot bake process. A cooling inert gas is then flown onto the wafer backside and an etchant gas is flown into the chamber to conduct a dry etch process for forming a via opening in the wafer.

Abstract: A method of forming very small silicon nitride spacers in split-gate flash EPROMs is disclosed which prevent the occurrence of “write disturb”, unwanted reverse tunneling, or erasing. This is accomplished by forming spacers with well controlled dimensions and well defined shapes through a judicious combination of dry etch with wet over-etch technique. The wet etch along with the dry etch widens the process window from a few seconds to several minutes so that the small dimensioned silicon nitride spacers can be better controlled than it has been possible in the past. In a second embodiment, the step of over-etching of the spacers is combined with the step of stripping off of an implant photomask, thus, shortening the manufacturing product cycle.

Abstract: A method for manufacturing capacitors is disclosed. The method is applicable to a capacitor whose upper electrode area is smaller than the lower electrode area. It is featured in that a material, such as a TiN hard mask, is inserted between the conventional electrode metal layer and photo resist layer. This enables one to perform the in-situ photo resist layer removal step after dry etching the upper electrode metal. Since the photo resist layer removal step uses oxygen plasma, the surface of the lower electrode polysilicon is formed with a protective oxide layer because the dielectric layer is etched during the process of dry etching the upper electrode metal. Using the disclosed method can solve the corrosion problem on the upper electrode metal and avoid the lower electrode polysilicon from being corroded by the wet etchant.

Abstract: A process for creating a fuse structure opening in a stack of materials comprised with overlying dielectric layers, and comprised with an underlying polysilicon layer, to expose a conductive fuse structure, has been developed. The process initiates with a dry etching procedure used to create an initial fuse structure opening in the dielectric layers, using a photoresist shape as an etch mask. Subsequent removal of the photoresist shape results in the completion of the fuse structure opening via in situ etching of the polysilicon layer exposed in the initial fuse structure opening. The isotropic wet etch procedure used for photoresist removal and in situ patterning of polysilicon, avoids polysilicon spacer formation on the sides of the conductive fuse structure, which would have been present with the use of an all dry etch procedure. In addition the wet etch procedure selectively terminates on a thin silicon oxide layer, located on the underlying conductive fuse structure.

Abstract: A method for in-situ descum/hot bake/dry etch a polyimide photoresist layer and a passivation layer in a singe process chamber is disclosed. A process chamber that can be used for conducting in-situ a descum, a hot bake and a dry etch process sequentially in the same chamber is also disclosed. In the method, a process chamber equipped with a wafer platform and a wafer backside heating and cooling device is first provided, followed by the step of positioning a wafer that has a passivation layer and a patterned polyimide photoresist layer on top of the platform. An oxygen plasma is then generated in the chamber cavity to conduct a descum process, followed by flowing a heated inert gas onto a backside of the wafer to conduct a hot bake process. A cooling inert gas is then flown onto the wafer backside and an etchant gas is flown into the chamber to conduct a dry etch process for forming a via opening in the wafer.

Abstract: The invention teaches the removal of dust particles during semiconductor processing without the need to modify the processing chambers or to wait until they are not being used for their normal purposes. The dust removal operation is performed inside loadlocks instead the processing chambers. Dust removal, in a loadlock, is accomplished by first initiating a flow of gas over the wafer surface. Then a negative charge is induced at the surface for a period of time followed by the induction of a positive charge. This causes the charged particles to be repelled away from the surface, at which point they are swept away by the gas. To remove the electrically neutral dust particles, the induced surface charge is switched too rapidly for these particles to follow, so they are briefly repelled from the surface and then swept away by the gas.

Abstract: An electrically conductive workpiece such as a semiconductor wafer or the like is transported between a staging area and an electrostatic chuck within a processing chamber using an electrostatic arm. The arm is used to apply an electrical charge to the wafer and to hold the wafer during transport by means of an electrostatic force of attraction between the arm and the wafer. The arm also pre-charges the wafer in preparation to be electrostatically chucked within the processing chamber. Pre-charging the wafer eliminates the need for using a gas plasma within the chamber for chucking and dechucking the wafer.

Abstract: A method to prevent threshold shifts in MOS transistors due to auto-doping from heavily doped polysilicon layers. Isolation regions are provided in a semiconductor substrate separating active areas. A gate oxide layer is formed over the surface of the semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A tungsten silicide layer is deposited overlying the polysilicon layer. The tungsten silicide layer and the first polysilicon layer are etched to form MOS gates and bottom electrodes for dual polysilicon capacitors. An interpoly dielectric layer is deposited overlying entire surface of the semiconductor substrate. A doped polysilicon layer is deposited overlying the interpoly dielectric layer. A sealing oxide layer is deposited overlying the doped polysilicon layer to prevent out-diffusion of impurity ions into the semiconductor substrate and thereby preventing auto-doping. The tungsten silicide layer is annealed. Ions are implanted to form drain and source regions.

Abstract: An electrostatic arm transports a semiconductor wafer between a staging area and a processing chamber and also electrically charges the wafer in order to eliminate the need for using gas plasma in the chamber to chuck and dechuck the wafer. The arm includes a pair of electrically conductive members coupled with an electrical power supply which respectively control the polarity of the charge applied to the wafer and create an electrostatic force which holds the wafer on the arm without the need for mechanical clamping. One of the members comprises a plate spaced from the face of the wafer by an air gap, and when charged with a polarity opposite that of the wafer, creates an electrostatic attraction force which holds the wafer the carrier. A controller is used to selectively reverse the polarity of charge on the plate so as to create an electrostatic repulsion force which positively releases the wafer from the carrier.

Abstract: A method for operating a plasma processing system comprises the following steps. Produce a plasma in a plasma processing chamber operating upon a selected workpiece. Perform in situ detection of electromagnetic radiation of a certain wavelength generated in the plasma in the plasma processing chamber. Calculate a first intensity difference of the certain wavelength from a set point of intensity. Halt production of the plasma in the plasma processing chamber if the first intensity difference is outside of specifications.

Abstract: Real time monitoring of a plasma etching process is performed by monitoring the intensity of a specific wavelength created by the plasma. Changes in the intensity of the plasma wavelength indicate the end-point in time for the process. The end-point value is compared with one or more reference values to determine whether the etching process is stable. End-point values outside of a pre-selected range of values is indicative of unstable processing conditions, thus allowing termination of the etching process before unstable conditions can result in substantial scrap.

Abstract: A method and apparatus to improve process control during plasma etching of semiconductor substrates. Improvements are directed towards controlling the rate of etching when using consumable electrodes. Consumable electrode materials are used to increase selectivity in certain plasma etching processes as in via. contact. or in SOG etch. A consumable electrode material has a significant effect on processing time due to changing gap dimension between electrodes. This invention teaches how to adjust for process variables by using feedback from two strategically placed pressure manometers.

Abstract: A workpiece with a back surface and a front surface has a layer formed on the front surface thereof which is to be etched by plasma etching. The workpiece is placed on a lower electrode in a plasma etching system with the back surface resting on the lower electrode. The workpiece is clamped to the lower electrode. A gas circulation system is formed in the surface of the lower electrode to supply heated gas, under pressure, to the back surface of a workpiece placed thereon to cause the workpiece to bow thereby forming a vaulted space below the workpiece. Then, while heating the back of the workpiece in this way, plasma etching of the layer upon the workpiece is performed.

Abstract: A method and apparatus for monitoring condition of the plasma of a plasma process during processing is disclosed. A spectrum detector (12) detects the intensity of a predetermined wavelength of radiation produced by the plasma process. The output of the spectrum detector is sampled, filtered, and normalized. A parameter calculator (20) calculates a parameter such as velocity or acceleration of the intensity. The calculated parameter is compared to a predetermined threshold. If the parameter exceeds the predetermined threshold, an error condition is indicated.

Abstract: A method and apparatus to improve process control during plasma etching of semiconductor substrates. Improvements are directed towards controlling the rate of etching when using consumable electrodes. Consumable electrode materials are used to increase selectivity in certain plasma etching processes as in via. contact. or in SOG etch. A consumable electrode material has a significant effect on processing time due to changing gap dimension between electrodes. This invention teaches how to adjust for process variables by using feedback from two strategically placed pressure manometers.

Abstract: The invention teaches the removal of dust particles during semiconductor processing without the need to modify the processing chambers or to wait until they are not being used for their normal purposes. The dust removal operation is performed inside loadlocks instead the processing chambers. Dust removal, in a loadlock, is accomplished by first initiating a flow of gas over the wafer surface. Then a negative charge is induced at the surface for a period of time followed by the induction of a positive charge. This causes the charged particles to be repelled away from the surface, at which point they are swept away by the gas. To remove the electrically neutral dust particles, the induced surface charge is switched too rapidly for these particles to follow, so they are briefly repelled from the surface and then swept away by the gas.

Abstract: A workpiece with a back surface and a front surface has a layer formed on the front surface thereof which is to be etched by plasma etching. The workpiece is placed on a lower electrode in a plasma etching system with the back surface resting on the lower electrode. The workpiece is clamped to the lower electrode. A gas circulation system is formed in the surface of the lower electrode to supply heated gas, under pressure, to the back surface of a workpiece placed thereon to cause the workpiece to bow thereby forming a vaulted space below the workpiece. Then, while heating the back of the workpiece in this way, plasma etching of the layer upon the workpiece is performed.