Abstract: An atomic layer deposition system is provided, including: a main body, a platform, a gas distribution showerhead assembly and a first ring member. The main body defines a reaction chamber, and the platform is located in the reaction chamber. The gas distribution showerhead assembly is disposed on the main body and includes at least one gas inlet channel and at least one gas diffusion plate. Each of the at least one gas diffusion plate includes a plurality of through holes. The first ring member defines a radial direction and is disposed between the platform and the at least one gas diffusion plate. A region of the at least one gas diffusion plate distributed with the plurality of through holes defines an outermost distribution profile. An inner circumferential wall of the first ring member and the outermost distribution profile keep a distance in the radial direction.

Abstract: A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: The semiconductor structure includes a die, a dielectric layer surrounding the die, a photoelectric device disposed adjacent to the die and surrounded by the dielectric layer, a first opening extending through the redistribution layer and configured to receive a light-conducting member, and a metallic shield extending at least partially through the redistribution layer and surrounding the first opening. A method for forming a semiconductor structure includes receiving a die; forming a dielectric layer to surround the die; and disposing a photoelectric device surrounded by the dielectric layer; forming a redistribution layer over the die, the dielectric layer and the photoelectric device; and removing a portion of the redistribution layer to form a first opening over the photoelectric device. A metallic shield extending at least partially through the redistribution layer and surrounding the first opening is formed during the formation of the redistribution layer.

Abstract: A computing system performs shared cache allocation to allocate cache resources to groups of tasks. The computing system monitors the bandwidth at a memory hierarchy device that is at a next level to the cache in a memory hierarchy of the computing system. The computing system estimates a change in dynamic power from a corresponding change in the bandwidth before and after the cache resources are allocated. The allocation of the cache resources are adjusted according to an allocation policy that receives inputs including the estimated change in the dynamic power and a performance indication of task execution.

Abstract: A computing system performs partial cache deactivation. The computing system estimates the leakage power of a cache based on operating conditions of the cache including voltage and temperature. The computing system further identifies a region of the cache as a candidate for deactivation based on cache hit counts. The computing system then adjusts the size of the region for the deactivation based on the leakage power and a bandwidth of a memory hierarchy device. The memory hierarchy device is at the next level to the cache in a memory hierarchy of the computing system.

Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.

Abstract: An array of complementary die sets is attached to a carrier substrate. A continuous complementary-level molding compound layer is formed around the array of complementary die sets. An array of primary semiconductor dies is attached to the array of complementary die sets. A continuous primary-level molding compound layer is formed around the array of primary semiconductor dies. The bonded assembly is diced by cutting along directions that are parallel to edges of the primary semiconductor dies. The sidewalls of the complementary dies are azimuthally tilted relative to sidewalls of the primary semiconductor dies, or major crystallographic directions of a single crystalline material in the carrier substrate are azimuthally tilted relative to sidewalls of the primary semiconductor dies.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Abstract: Disclosed are an isolation method for a high-performance computer system, and a high-performance computer system. The isolation method comprises node-level isolation performed. The node-level isolation comprises: configuring a routing table for each computing node, and configuring, in the routing table, valid routing information for computing node pairs; when any one source computing node needs to communicate with a target computing node, determining, by lookup, whether valid routing information exists between the source computing node and the target computing node according to the configured routing table; if so, allowing the source computing node to communicate with the target computing node; otherwise, forbidding the source computing node from communicating with the target computing node.

Abstract: An SoC architecture includes a non-volatile memory and an SoC chip. The SoC chip is connected with the non-volatile memory. The SoC chip includes a central processing unit, a volatile memory, a system bus, an on-the-fly decryption circuit, a memory interface, a timer and a key bank. The on-the-fly decryption circuit is connected with the key bank. The on-the-fly decryption circuit performs an encryption operation or a decryption operation according to plural keys in the key bank. After the SoC architecture is powered on, if the timer is not disabled and the timer has counted time for a specified time period, the central processing unit is subjected to a warm reset, and a storage format in the non-volatile memory is changed from an initial format to an operation format by the central processing unit.

Abstract: This application relates to a communication method based on a virtual role interaction interface, including: displaying a virtual role interaction interface of a virtual role interaction application, the virtual role interaction interface including a target virtual role identifier; displaying an instant session message triggering control on the virtual role interaction interface in response to a trigger operation on the target virtual role identifier; displaying a message input interface in response to a trigger operation on the instant session message triggering control; and transmitting, to an instant messaging user account corresponding to the target virtual role identifier after a session message is inputted in the message input interface, the session message used for displaying on an instant messaging application.

Abstract: An operating method with goods information is applicable to an electronic device. The operation method includes: obtaining image information associated with one or more goods objects on a target electronic shelf among a plurality of electronic shelves in a network; and performing first communicating with a server for controlling the electronic shelves in the network according to either or both of the image information and feature information associated with the one or more goods objects, wherein feature information is extracted from the image information and the first communicating includes wirelessly transmitting either or both of the image information and the feature information associated with the one or more goods objects to the server.

Abstract: A neurostimulation device 1 for non-destructively stimulating neural activity in a nerve 3 in proximity to a blood vessel 5. The neurostimulation device 1 comprises a catheter 7 for insertion into the blood vessel 5; a proximal electrode 11 offset from a distal electrode 9 along a length of the catheter 7; and an insulator 13 positioned between the proximal electrode 11 and the distal electrode 9 on the catheter 7. The insulator 13 has a contracted configuration in which the size of the insulator 13 allows the catheter 7 to travel inside the blood vessel 5. The insulator 13 has an expanded configuration in which the insulator 13 blocks blood flowing through the blood vessel between the proximal electrode 11 and the distal electrode 9.

Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.

Abstract: Provided are systems and methods for indicating deployment of application features. In one embodiment, a method is provided that includes determining available features of a current deployment of an application for receiving machine-generated data from one or more data sources of a data system, determining un-deployed features of the current deployment of the application, wherein the un-deployed features comprise one or more of the available features that is configured to use input data from a data source and wherein the input data is not available to the feature in the current deployment of the application, and causing display of a deployment graphical user interface (GUI) that comprises an indication of the un-deployed features.

Abstract: A grip device for a pole includes a grip and a wrist strap unit. The grip has a connecting part that defines a connecting space therein, and that has a lower portion and a protruding portion disposed in the connecting space. The wrist strap unit includes a connecting member that engages removably the connecting space, and that has a tail part. The tail part is pivotable between a locked position, where the tail part is adjacent to the lower portion so that the connecting member is retained in the connecting space by the protruding portion, and an unlocked position, where the tail part is away from the lower portion and the protruding portion so that the connecting member is permitted to be separated from the connecting part.