Abstract: A detection device for measuring an antenna is disclosed, wherein the detection device is provided with a probe seat made of a reflected wave absorbent material; a front end of the probe seat is provided with an extending front arm for connecting to a probe; and a rear end of the probe seat is provided with a connector, of which one end is for connecting to a detection instrument and the other end is electrically connected to the probe through the front arm, thereby when measuring an antenna, the probe seat can absorb reflected waves from the antenna to measure the quality of the antenna pattern.

Abstract: A detection device for measuring an antenna is disclosed, wherein it is provided with a probe seat made of a metal material; a front end of the probe seat is provided with an extending front arm for connecting to a probe; and a rear end of the probe seat is provided with a connector, of which one end is for connecting to a detection instrument and the other end is electrically connected to the probe through the front arm; the detection device is characterized in that an outer surface of the probe seat is covered by a wave absorbent material capable of absorbing reflected waves, thereby when measuring an antenna, the probe seat can absorb reflected waves from the antenna to measure the quality of the antenna pattern.

Abstract: A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.

Abstract: A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

Abstract: A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space

Abstract: A blood-glucose meter integrated with a biological test-piece tank includes a biological test-piece tank and a blood-glucose meter. The biological test-piece tank has internally a chamber for providing an accommodation room to store a plurality of biological test pieces, a tank opening located at a top thereof to pair a cover so as to form a sealed structure, and a tank bottom located by opposing to the cover. The blood-glucose meter, connected with the tank bottom, has an inserting hole for receiving a biological test piece that carries thereon a biological specimen to be examined for obtaining a corresponding blood-glucose value.

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract: An electronic device includes a first microphone, a second microphone, a sensing unit, and a control unit. The first and second microphones are respectively positioned at two different sides of the electronic device. The sensing unit is configured to sense a first light value of a first side of the electronic device, a second light value of a second side of the electronic device and an orientation of the electronic device. The control unit is configured to select one of the first microphone and the second microphone to work according to the first and second light values and the orientation of the electronic device.

Abstract: A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.

Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

Abstract: A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.

Abstract: A multi-chip package comprising: an interconnection substrate comprising an interconnection bridge embedded in the interconnection substrate, and an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection layer and the interconnection bridge, and a polymer layer between the first and second interconnection metal layers, wherein the interconnection bridge is embedded in the interconnection scheme and has sidewalls surrounded by the polymer layer; a semiconductor IC chip over the interconnection substrate and across over an edge of the interconnection bridge; a memory chip over the interconnection substrate and across over an edge of the interconnection bridge, wherein the interconnection bridge comprises a plurality of metal interconnects configured for a data bus coupling the semiconductor IC chip to the memory chip, wherein a bitwidth of the data bus between the semiconductor IC chip and the memory chip is greater than or equa

Abstract: An electronic device includes a keyboard module, a silicone film, a light-emitting module, and a touch module. The keyboard module has a plurality of buttons and a point stick. The silicone film has a virtual touch region. The light-emitting module is configured below the silicone film and corresponds to the virtual touch region. The light-emitting module includes a first light-emitting unit and a second light-emitting unit. The touch module is configured below the silicone film and corresponds to the virtual touch region. The touch module includes a control chip and a sensing layer. The point stick, the first light-emitting unit, the second light-emitting unit, and the sensing layer are electrically connected to the control chip, respectively.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

Abstract: An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

Abstract: This present invention discloses an image guided augmented reality method, comprising the following steps of: obtaining a first conversion matrix of a camera and a marked point; obtaining a second conversion matrix of the eye and the camera; linking the first conversion matrix and the second conversion matrix to obtain a correct position corresponding matrix of the eye to the marked point; and linking the correct position corresponding matrix to a position feature of the marked point to obtain the correct position of the eye to the marked point. The present invention also discloses a surgical navigation method of wearable glasses, used for obtaining the correct position of the operator's eye to the marked point.

Abstract: A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Abstract: A bloom filter and an implementation method thereof are provided. The implementation method has a ternary rule encoded as a rule binary codeword according to a predetermined encoding rule; has a packet encoded as at least one packet binary codeword according to the predetermined encoding rule; and comparing the rule binary codeword and the at least one packet binary codeword to decide a following processing of the packet. The predetermined encoding rule includes: tagging 0 or 1 into most significant bit (MSB) of the output binary codeword based on mask length of the input codeword; placing the prefix of the input codeword right after MSB of the output binary codeword; and tagging a string to last bits of the output binary codeword based on the mask length, and the bit number of the string equals to the mask length.