Patents by Inventor Yuan Li

Yuan Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11928503
    Abstract: Embodiments are directed to deploying a workload on the best/highest performance node. Nodes configured to accommodate a request for a workload are selected. Information is collected on each of the selected nodes and the workload. Predicted response times expected for the workload running on each of the selected nodes are determined. The workload is deployed on a node of the selected nodes, the node having a corresponding predicted response time for the workload, the workload being deployed on the node based at least in part on the corresponding predicted response time.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Qi Feng Huo, Yuan Yuan Wang, Da Li Liu, Lei Li, Yan Song Liu
  • Patent number: 11927864
    Abstract: A display may include illumination optics, a ferroelectric liquid crystal on silicon (fLCOS) panel, and a waveguide. The illumination optics may produce illumination that is modulated by the fLCOS panel to produce image light. The waveguide may direct the image light towards an eye box. The fLCOS panel may include a ferroelectric liquid crystal (fLC) layer and a backplane. In order to maximize the reflectance of the fLCOS panel and thus the optical performance of the display, the backplane may be a silver backplane or a dielectric mirror backplane. In addition, the backplane may have a cell gap that is equal to a wavelength divided by four times the birefringence of the fLC layer. In order to further optimize the optical performance of the display module, the wavelength used in determining the cell gap may be a green wavelength between 500 nm and 565 nm.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: March 12, 2024
    Inventors: Yuan Chen, Xiaokai Li, Zhibing Ge
  • Patent number: 11928127
    Abstract: In response to receiving a request for an identity key from a first entity, an identity key for the first entity is generated. A first request from the first entity to replicate a set of data is received. The generated identity key for the first entity is added to the metadata of the set of data requested to be replicated. A determination is made whether a replication rule exists for the first entity. In response to determining that a replication rule exists for the first entity, the set of data is replicated according to the replication rule for the first entity.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Xin Wang, Yong Zheng, Xue Sheng Li, Li Xia Liu, Fang Yuan Cheng, Shuo Feng
  • Patent number: 11930333
    Abstract: In certain aspects, a noise suppression method and system for a personal sound amplification product (PSAP) are disclosed. An environmental audio signal acquired through one or more microphones is processed to generate a set of first sub-band signals in a set of first sub-bands. The environmental audio signal is also processed to generate a set of second sub-band signals in a set of second sub-bands. A set of first gains for the set of first sub-band signals in the set of first sub-bands is determined based on the set of second sub-band signals in the set of second sub-bands. The set of first sub-band signals is processed based on the set of first gains to generate a noise-suppressed audio signal.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: March 12, 2024
    Assignee: BESTECHNIC (SHANGHAI) CO., LTD.
    Inventors: Qian Li, Yuan Jiang, Xingqiang Wu
  • Patent number: 11928824
    Abstract: An approach is provided in which the approach receives an image that includes multiple image points and constructs a plane in the image based on a first subset of the plurality of image points. The approach identifies a second subset of the image points that belong to the plane and are not part of the first subset of image points, and removes the first subset of image points and the second subset of image points form the image points. The approach annotates the remaining subset of image points in the image.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Xue Ping Liu, Dan Zhang, Yuan Yuan Ding, Chao Xin, Fan Li, Hong Bing Zhang, Xu Min
  • Publication number: 20240077608
    Abstract: Disclosed are a method and system for evaluating sonar self-noise at a ship design stage. The method includes: building a ship structure full-scale geometric simulation model; acquiring loss factors and sonar transducer space outfitting acoustic absorption coefficient material parameters; acquiring mechanical excitation, hydrodynamic excitation, and propeller excitation; inputting the loss factors and the sonar transducer space outfitting acoustic absorption coefficient material parameters into an established statistical energy evaluation model, and applying a mechanical excitation to a face plate of foundation of the built ship structure full-scale geometric simulation model, applying a hydrodynamic excitation to the surface of a ship hull, and applying a propeller excitation to a stern shaft to perform calculation of sonar self-noise of a ship to obtain total spectral density level of the sonar self-noise; and evaluating spectral density level calculation results by index requirements.
    Type: Application
    Filed: October 24, 2023
    Publication date: March 7, 2024
    Inventors: Haichao LI, Jiawei XU, Fuzhen PANG, Cong GAO, Yuhang TANG, Jiajun ZHENG, Xueren WANG, Zhe ZHAO, Xuhong MIAO, Yuan DU
  • Publication number: 20240079268
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 7, 2024
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Publication number: 20240080381
    Abstract: Disclosed are a rotating shaft mechanism and a foldable mobile terminal. The rotating shaft mechanism provided in the embodiments of this application is mainly applied to a foldable mobile terminal, so as to implement unfolding and folding of two main body parts of the foldable mobile terminal. When the elastic support member is in a compressed state, at least some segments of the first part and the second part overlap in a floating direction, and the second part provides a compressed deformation space for a part or all of the first part. In this way, a height of the elastic support member in overall compression and deformation is reduced, and an ultra-thin design requirement of the foldable mobile terminal is met.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 7, 2024
    Inventors: Yaolei ZHANG, Mingqian GAO, Guotong ZHOU, Yuan WANG, Haifei LI
  • Publication number: 20240076103
    Abstract: Disclosed is a part packaging device. The part packaging device comprises a machine body, wherein a sliding groove and a groove are symmetrically formed in the inner wall of the machine body, a placing plate is installed in the machine body, a sliding block and a lifting block are symmetrically installed on the two sides of the placing plate, the sliding block is slidably installed in the sliding groove, the lifting block is installed in the groove, a threaded rod is installed at the bottom of the interior of the groove, a lifting plate is installed in the machine body, and springs are installed between the bottom of the interior of the machine body and the lifting plate.
    Type: Application
    Filed: May 26, 2022
    Publication date: March 7, 2024
    Inventors: Guiyao LI, Yuan-Jie LI
  • Publication number: 20240079786
    Abstract: An electronic device may be provided with peripheral conductive housing structures, a first antenna, and a second antenna. A gap may divide the housing structures into a first segment forming an arm of the first antenna and a second segment forming an arm of the second antenna. A first feed terminal may be coupled to the first segment and a second feed terminal may be coupled to the second segment. Switchable components may be coupled in parallel between the first and second feed terminals across the gap. The switchable components may be adjusted to tune the frequency response of the first and/or second antenna. The switchable components may have a first state in which only the first feed terminal feeds the first antenna and may have a second state in which both the first and second feed terminals feed the first antenna.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 7, 2024
    Inventors: Han Wang, Aobo Li, Victor C Lee, Yuancheng Xu, Ahmed Ali Abdelhaliem Nafe, Enrique Ayala Vazquez, Yiren Wang, Yuan Tao, Christopher Q Ma, Zhiheng Zhou, Sherry Cao, Dale T Morgan, Timothy L Stickles, Hao Xu, Hongfei Hu, Mattia Pascolini
  • Publication number: 20240078441
    Abstract: A method for knowledge representation and deduction of service logic includes: generating, based on a knowledge representation model, a semantic graph corresponding to conceptual-layer service logic, where the semantic graph includes one or more types of nodes and edges for connecting the one or more types of nodes, and the nodes include at least a node of a variable type; generating, based on the semantic graph and a physical table to which a service object is mapped, an instance graph, where the instance graph includes the nodes and edges in the semantic graph; generating executable code based on a service logic relationship between the nodes in the instance graph; and determining, based on the executable code and a data instance corresponding to a node whose in-degree is 0 in the instance graph, a data instance corresponding to each node in the instance graph.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Inventors: Rong Duan, Kangxing Hu, Wenwen Huang, Yuan Yuan, Wen Peng, Chunxi Liu, Qinjie Yang, Xiaoliang Yin, Shufan Li
  • Patent number: 11923399
    Abstract: A micro light-emitting diode display panel includes a substrate, at least one light-emitting element, a reflective layer and a light-absorbing layer. The at least one light-emitting element is disposed on the substrate to define at least one pixel, and each light-emitting element includes micro light-emitting diodes. The reflective layer is disposed on the substrate and located between the micro light-emitting diodes. The reflective layer has cavities surrounding the micro light-emitting diodes, such that a thickness of a portion of the reflective layer close to any one of the micro light-emitting diodes is greater than a thickness of a portion of the reflective layer away from the corresponding micro light-emitting diode. The light-absorbing layer is at least disposed in the cavities of the reflective layer.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: March 5, 2024
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Sheng-Yuan Sun, Loganathan Murugan, Po-Wei Chiu, Yun-Li Li
  • Patent number: 11919824
    Abstract: Disclosed are a silicon nitride ceramic sintered body and preparation method thereof. The silicon nitride ceramic sintered body includes a sintered bulk and a hard surface layer having a thickness of 10-1000 ?m, formed on a surface of the sintered bulk, wherein the sintered bulk comprises a first silicon nitride crystalline phase and a first grain boundary phase; the hard surface layer comprises a second silicon nitride crystalline phase and a second grain boundary phase; the first grain boundary phase comprises a metal tungsten phase being tungsten elementary substance and/or a tungsten alloy; the second grain boundary phase comprises tungsten carbide particles; tungsten element in the metal tungsten phase accounts for 80-100 wt % of total tungsten element in the first grain boundary phase; and tungsten element in the tungsten carbide particles accounts for 60-100 wt % of total tungsten element in the second grain boundary phase.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: March 5, 2024
    Assignees: Lanzhou Institute of Chemical Physics, CAS, Yantai Zhongke Research Institute of Advanced Materials and Green Chemical Engineering, Shandong Laboratory of Yantai Advanced Materials and Green Manufacturing
    Inventors: Zhuhui Qiao, Lujie Wang, Tongyang Li, Ziyue Wang, Yuan Yu, Huaguo Tang
  • Patent number: 11918987
    Abstract: Provided are a preparation method for a propylene epoxidation catalyst, and a use thereof. During the preparation, an alkoxide solution of a prepared active component and a silica gel support are mixed, then a rotary evaporation treatment is performed on the mixture to remove a low-carbon alcohol to obtain a catalyst precursor, and then the obtained catalyst precursor is subjected to calcination and silylation treatments to obtain the propylene epoxidation catalyst. The catalyst is prepared in a simple process, can be applied to the chemical process of preparing propylene oxide by propylene epoxidation, has high average selectivity to propylene oxide, and has industrial application prospect.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: March 5, 2024
    Assignee: Wanhua Chemical Group Co., Ltd.
    Inventors: Lei Wang, Tongji Wang, Fei Ye, Kang Sun, Naibo Chu, Qiankun Jiao, Yuan Li
  • Patent number: 11922643
    Abstract: A method for intelligently measuring vehicle speed based on a binocular stereo vision system includes: training a Single Shot Multibox Detector neural network to obtain a license plate recognition model; calibrating the binocular stereo vision system to acquire parameters of two cameras; detecting the license plates in the captured video frames with the license plate recognition model, locating the license plate position; performing feature point extraction and stereo matching by a feature-based matching algorithm; screening and eliminating the matching point pairs, and reserving the coordinates of the matching point pair closest to the license plate center; performing stereo measurement on the screened matching point pair to get the spatial coordinates of the position; calculating and obtaining the speed of the target vehicle.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: March 5, 2024
    Inventors: Lei Yang, Xiaowei Song, Menglong Li, Yuan Li, Wenjing Cai, Jianchen Luo
  • Patent number: 11922058
    Abstract: Embodiments of a three-dimensional (3D) memory device and a method of operating the 3D memory device are provided. The 3D memory device includes an array of 3D NAND memory cells, an array of static random-access memory (SRAM) cells, and a peripheral circuit. The array of SRAM cells and the peripheral circuit arranged at one side are bonded with the array of 3D NAND memory cells at another side to form a chip. Data is received from a host through the peripheral circuit, buffered in the array of SRAM cells, and transmitted from the array of SRAM cells to the array of 3D NAND memory cells. The data is programmed into the array of 3D NAND memory cells.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: March 5, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yue Ping Li, Wei Jun Wan, Chun Yuan Hou
  • Patent number: 11923205
    Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: March 5, 2024
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Ju Li, Ang Chan, Hsin-Jung Liu, Wei-Xin Gao, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-Ming Lai, Fu-Shou Tsai
  • Publication number: 20240073303
    Abstract: This application provides a folding assembly and a foldable electronic device. The folding assembly is applied to a foldable electronic device, and is configured to carry a flexible display screen. The folding assembly includes a shaft base, a first housing, and a second housing. The first housing and the second housing are respectively disposed on both sides of the shaft base. A door plate swing arm is located above the shaft base and is disposed on each of both sides of a center line of the shaft base, one end of each door plate swing arm is rotatably connected to the shaft base, and the other end of each door plate swing arm is rotatably connected to the first housing or the second housing.
    Type: Application
    Filed: January 11, 2022
    Publication date: February 29, 2024
    Inventors: Yaolei ZHANG, Zhengping TAN, Mingqian GAO, Yuan WANG, Haifei LI, Guotong ZHOU, Leibo YUAN, Bin YAN, Kuibing ZHAO
  • Publication number: 20240071988
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate and a dielectric layer on the substrate; forming a hole in the dielectric layer; forming an initial barrier material layer and a conductive layer on an upper surface of the dielectric layer and in the hole; removing part of the initial barrier material layer and part of the conductive layer to form a barrier material layer and a via element in the hole respectively and expose the upper surface of the dielectric layer. An upper surface of the barrier material layer is higher than the upper surface of the dielectric layer.
    Type: Application
    Filed: October 11, 2022
    Publication date: February 29, 2024
    Inventors: Kun-Ju LI, Hsin-Jung LIU, Wei-Xin GAO, Jhih-Yuan CHEN, Ang CHAN, Chau-Chung HOU
  • Publication number: 20240073100
    Abstract: Disclosed are an isolation method for a high-performance computer system, and a high-performance computer system. The isolation method comprises node-level isolation performed. The node-level isolation comprises: configuring a routing table for each computing node, and configuring, in the routing table, valid routing information for computing node pairs; when any one source computing node needs to communicate with a target computing node, determining, by lookup, whether valid routing information exists between the source computing node and the target computing node according to the configured routing table; if so, allowing the source computing node to communicate with the target computing node; otherwise, forbidding the source computing node from communicating with the target computing node.
    Type: Application
    Filed: June 27, 2023
    Publication date: February 29, 2024
    Applicant: NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY
    Inventors: Pingjing LU, Mingche LAI, Zeyu XIONG, Jinbo XU, Junsheng CHANG, Xingyun QI, Zhang LUO, Yuan LI, Yan SUN, Yang OU, Zicong WANG, Jianmin ZHANG