Patents by Inventor Yuan Liao

Yuan Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Amplifier and method of operating same
    Patent number: 9917555
    Abstract: An amplifier includes an input node, an output node, a transistor and a transformer. The input node is configured to receive a first signal. The output node is configured to output an amplified first signal. The transistor includes a first terminal, a second terminal and a third terminal. The first terminal is coupled to the input node and a first supply voltage source. The second terminal is coupled to a second supply voltage source and the output node. The third terminal is coupled to a reference node. The transformer is coupled to the first terminal and the third terminal. The transistor is configured to operate in a sub-threshold region and a near-triode region.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: March 13, 2018
    Assignee: TWAIWAN SEMICONDUCTOR MANUFACTORING COMPANY, LTD.
    Inventors: Jun-De Jin, Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Ying-Ta Lu
  • SYSTEM AND METHOD FOR MANAGING CWSN WITH GUI
    Publication number: 20180069745
    Abstract: A system and method for managing CWSN with GUI are disclosed. The system comprises a cloud server to managing sensor data and operation status of a wireless sensor network. The system also comprises a client communicating with the cloud server to generate a dynamic user interface mainly in graphics for monitoring and instruction exchange. It can make the information of the wireless sensor network easy to access for users and provide more convenient control and maintenance of the wireless sensor network.
    Type: Application
    Filed: July 30, 2013
    Publication date: March 8, 2018
    Inventors: Yu WANG, Yuan LIAO, Haibo LU
  • METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20180012975
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.
    Type: Application
    Filed: August 15, 2017
    Publication date: January 11, 2018
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Wei-Hao Huang
  • Semiconductor device and fabrication method thereof
    Patent number: 9865593
    Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: January 9, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Hsiang-Hung Peng, Wei-Hao Huang, Ching-Wen Hung, Chih-Sen Huang
  • DEVICE WITH REINFORCED METAL GATE SPACER AND METHOD OF FABRICATING
    Publication number: 20180006133
    Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.
    Type: Application
    Filed: August 29, 2017
    Publication date: January 4, 2018
    Inventors: Chia-Lin Liu, Yu-Cheng Tung, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Transistor with Asymmetric Source and Drain Regions
    Publication number: 20170345930
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Application
    Filed: November 2, 2016
    Publication date: November 30, 2017
    Inventors: HSIEN-YUAN LIAO, CHIEN-CHIH HO, CHI-HSIEN LIN, HUA-CHOU TSENG, HO-HSIANG CHEN, RU-GUN LIU, TZU-JIN YEH, YING-TA LU
  • Manufacturing method for forming a semiconductor structure
    Patent number: 9799550
    Abstract: The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: October 24, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hao Huang, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen, Shang-Yuan Tsai
  • Manufacturing method of semiconductor device
    Patent number: 9793382
    Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: October 17, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Hsien Lin, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Device with reinforced metal gate spacer and method of fabricating
    Patent number: 9780193
    Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: October 3, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chia-Lin Lu, Yu-Cheng Tung, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Semiconductor device and method of fabricating the same
    Patent number: 9773890
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: September 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Wei-Hao Huang
  • METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE WITH DOPED HARD MASK
    Publication number: 20170263744
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 14, 2017
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Wei-Hao Huang
  • Semiconductor device
    Patent number: 9748349
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around the gate structure; a first contact plug in the ILD layer; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and a spacer between the second contact plug and the second dielectric layer.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 29, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen, Wei-Hao Huang
  • Semiconductor device and method for fabricating the same
    Patent number: 9728455
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: August 8, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen
  • Semiconductor device and method for fabricating the same
    Patent number: 9711411
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: July 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Shih-Fang Tzou, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Wei-Hao Huang
  • MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    Publication number: 20170200811
    Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.
    Type: Application
    Filed: March 28, 2017
    Publication date: July 13, 2017
    Inventors: Chia-Lin Lu, Chun-Hsien Lin, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Semiconductor device having gate structure with doped hard mask
    Patent number: 9698255
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: July 4, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Wei-Hao Huang
  • Multi-gate and complementary varactors in FinFET process
    Patent number: 9698146
    Abstract: A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hsien Lin, Ying-Ta Lu, Hsien-Yuan Liao, Ho-Hsiang Chen, Chewn-Pu Jou, Fu-Lung Hsueh
  • AMPLIFIER AND METHOD OF OPERATING SAME
    Publication number: 20170179894
    Abstract: An amplifier includes an input node, an output node, a transistor and a transformer. The input node is configured to receive a first signal. The output node is configured to output an amplified first signal. The transistor includes a first terminal, a second terminal and a third terminal. The first terminal is coupled to the input node and a first supply voltage source. The second terminal is coupled to a second supply voltage source and the output node. The third terminal is coupled to a reference node. The transformer is coupled to the first terminal and the third terminal. The transistor is configured to operate in a sub-threshold region and a near-triode region.
    Type: Application
    Filed: August 16, 2016
    Publication date: June 22, 2017
    Inventors: Jun-De JIN, Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Ying-Ta LU
  • Method for manufacturing semiconductor device having metal gate
    Patent number: 9685531
    Abstract: A method for manufacturing a semiconductor device having metal gates includes following steps. A substrate including a first transistor and a second transistor formed thereon is provided. The first transistor includes a first gate trench and the second transistor includes a second gate trench. A patterned first work function metal layer is formed in the first gate trench and followed by forming a second sacrificial masking layer respectively in the first gate trench and the second gate trench. An etching process is then performed to form a U-shaped first work function metal layer in the first gate trench. Subsequently, a two-step etching process including a strip step and a wet etching step is performed to remove the second sacrificial masking layer and portions of the U-shaped first work function metal layer to form a taper top on the U-shaped first work function metal layer in the first gate trench.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Bidirectional hub assembly
    Patent number: 9669657
    Abstract: A bidirectional hub assembly includes an axle unit, a hub shell mounted on the axle unit, a driving unit mounted on the axle unit, and a plurality of right-hand-drive and left-hand-drive units that are mounted to the hub shell. Each of the right-hand-drive and left-hand-drive units has a pawl engageable with the driving unit. The bidirectional hub assembly serves as a right-hand-drive hub when the pawl of at least one of the right-hand-drive units is in an enabled state and the pawl of each of the left-hand-drive units is in a disabled state, and serves as a left-hand-drive hub when the pawl of at least one of the left-hand-drive units is in an enabled state and the pawl of each of the right-hand-drive units is in a disabled state.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: June 6, 2017
    Assignee: Kun Teng Industry Co., Ltd.
    Inventors: Hubert Chen, Yung-Yuan Liao