Patents by Inventor Yuan Liao

Yuan Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190206735
    Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device includes a substrate having a first conductive type. A second conductive type first epitaxial layer is disposed over the substrate. A second conductive type second epitaxial layer is disposed over the second conductive type first epitaxial layer. An active region of the substrate includes a first conductive type buried layer in the second conductive type first and second epitaxial layers. A first conductive type doped well region is disposed in the second conductive type second epitaxial layer. A second conductive type heavily doped region is disposed over the first conductive type doped well region. A first trench isolation feature is disposed in the substrate. In addition, a first conductive type doped region is disposed between a bottom surface of the first trench isolation feature and the first conductive type buried layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 4, 2019
    Inventors: Vivek NINGARAJU, Po-An CHEN, Ching-Yuan LIAO
  • Patent number: 10332978
    Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Yu-Cheng Tung, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Publication number: 20190190100
    Abstract: A heat dissipation device for a vehicle battery includes a box for receiving therein at least a vehicle battery; an upper lid disposed above the box and separated from the box by a waterproof plastic sheet; a microspray heat dissipation pipe disposed on a side of the box and having at least a microspray nozzle in communication with an inside of the box; and at least a non-return exhaust duct disposed on an opposing side of the box and in communication with the inside of the box.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: JING-HONG CHEN, WEI-YUAN LIAO, YU-HUNG CHEN, CHING-HSIANG WANG, CHIA-CHEN WU
  • Publication number: 20190184920
    Abstract: A vehicle battery device comprises a box for receiving therein at least a vehicle battery, wherein a fastening platform is disposed on an inner sidewall surface of the box, and support boards is disposed at a bottom of the fastening platform; an upper lid disposed above the box and separated from the box by a waterproof plastic sheet; and at least a quick-release unit comprising a screw, washer, spring, fixing board, and wedge-shaped fixing block, with the at least a quick-release unit fastened between the fastening platform and the vehicle battery, wherein a wedge-shaped recess is disposed on an upper surface of the vehicle battery, and a wedge-shaped fastening hole is disposed in the fixing board, allowing the wedge-shaped fixing block to penetrate the wedge-shaped fastening hole and engage with the wedge-shaped recess, thereby allowing the vehicle battery to be fixed in place inside the box.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: Jing-Hong Chen, Wei-Yuan Liao, Yu-Hung Chen, Ching-Hsiang Wang, Chia-Chen Wu
  • Publication number: 20190146186
    Abstract: An optical imaging lens assembly includes five lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element has an image-side surface being concave in a paraxial region thereof. The second lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The third lens element with positive refractive power has an image-side surface being convex in a paraxial region thereof. The fourth lens element has positive refractive power. The fifth lens element has negative refractive power.
    Type: Application
    Filed: April 12, 2018
    Publication date: May 16, 2019
    Applicant: LARGAN PRECISION CO.,LTD.
    Inventors: Cheng-Yuan LIAO, Shu-Yun YANG, Kuo-Jui WANG
  • Patent number: 10276716
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Yuan Liao, Chien-Chih Ho, Chi-Hsien Lin, Hua-Chou Tseng, Ho-Hsiang Chen, Ru-Gun Liu, Tzu-Jin Yeh, Ying-Ta Lu
  • Publication number: 20190103354
    Abstract: An integrated circuit includes an inductor over a substrate and a guard ring surrounding the inductor. The guard ring includes a first staggered line, a first metal line extending in a first direction and a second metal line extending in a second direction different from the first direction. The first staggered line has a first end coupled to the first metal line, and a second end coupled to the second metal line. The first staggered line includes a first set of vias, a first set of metal lines in a first metal layer and a second set of metal lines in a second metal layer different from the first metal layer. The first set of vias coupling the first set of metal lines with the second of second metal lines.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Inventors: Chiao-Han LEE, Hsien-Yuan LIAO, Ying-Ta LU, Chi-Hsien LIN, Ho-Hsiang CHEN, Tzu-Jin YEH
  • Publication number: 20190094498
    Abstract: An optical imaging lens assembly includes six lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. The second lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The fifth lens element has negative refractive power. The sixth lens element has positive refractive power.
    Type: Application
    Filed: January 10, 2018
    Publication date: March 28, 2019
    Applicant: LARGAN PRECISION CO.,LTD.
    Inventors: Cheng-Yuan LIAO, Shu-Yun YANG
  • Patent number: 10236824
    Abstract: A voltage controlled oscillator (“VCO”) circuit is disclosed. The VCO includes a switch module comprising a first transistor and a second transistor; a first LC-tank module, the first LC-tank module is operatively connected between the drain of the first transistor and the drain of the second transistor; and a second LC-tank module, the second LC-tank module is operatively connected between the gate of the first transistor and the gate of the second transistor, the source of the first transistor and the source of the second transistor are operatively connected.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: March 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jun-De Jin, Ying-Ta Lu, Hsien-Yuan Liao
  • Patent number: 10199374
    Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Hsiang-Hung Peng, Wei-Hao Huang, Ching-Wen Hung, Chih-Sen Huang
  • Patent number: 10192825
    Abstract: A semiconductor device includes a first gate line, a second gate line and a first bar-shaped contact structure. The first gate line has a first long axis extending along a first direction. The second gate line is parallel to the first gate line. The first bar-shaped contact structure has a second axis forming an angle substantially greater than 0° and less than 90° with the first long axis.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: January 29, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hao Huang, Chun-Lung Chen, Kun-Yuan Liao, Ying-Chih Lin, Chia-Lin Lu
  • Patent number: 10163779
    Abstract: An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiao-Han Lee, Hsien-Yuan Liao, Ying-Ta Lu, Chi-Hsien Lin, Ho-Hsiang Chen, Tzu-Jin Yeh
  • Publication number: 20180333754
    Abstract: A washing device includes a main body, a water system, and a drying system. The main body includes a first washing zone, a second washing zone, and a drying zone. A transporting device transports an object to make it pass through the first washing zone, the second washing zone, and the drying zone. The first washing zone has a first water outlet, and the second washing zone has a second water outlet. The water system includes a heater for heating water and a tank. A first pipe connects the heater and the first water outlet, and a second pipe connects the heater and the tank. An outlet pipe connects the tank and the second water outlet. A collecting structure collects waste water and injects into the tank. The drying system is adapted to supply air flow to the drying zone for drying the object.
    Type: Application
    Filed: February 20, 2018
    Publication date: November 22, 2018
    Inventor: PING-YUAN LIAO
  • Patent number: 10109525
    Abstract: A method for fabricating a semiconductor device is provided including providing a substrate, on which a plurality of elements is formed. A first inter-dielectric layer is formed over the substrate, covering the elements. A first plug structure is formed in the first inter-dielectric layer, including performing a polishing process over the first inter-dielectric layer to have a dishing on top and extending from a sidewall of the first plug structure. A hard mask layer is formed to fill the dishing. A second inter-dielectric layer is formed over the hard mask layer. A second plug structure is formed in the second inter-dielectric layer to electrically contact the first plug structure, wherein the second plug structure has at least an edge portion extending on the hard mask layer.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: October 23, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Jiunn-Hsiung Liao, Wei-Hao Huang, Kai-Teng Cheng
  • Patent number: 10103250
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Wei-Hao Huang
  • Patent number: 10097397
    Abstract: A system and method for managing CWSN with GUI are disclosed. The system comprises a cloud server to managing sensor data and operation status of a wireless sensor network. The system also comprises a client communicating with the cloud server to generate a dynamic user interface mainly in graphics for monitoring and instruction exchange. It can make the information of the wireless sensor network easy to access for users and provide more convenient control and maintenance of the wireless sensor network.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: October 9, 2018
    Assignee: GTI International Semiconductor Technology Co., Ltd.
    Inventors: Yu Wang, Yuan Liao, Haibo Lu
  • Patent number: 10062584
    Abstract: A method for forming a semiconductor structure is disclosed. The method includes the following steps. A first pattern structure and a second pattern structure are formed on a substrate. The second pattern structure is wider than the first pattern structure. Spacers are formed on sidewall surfaces of the first pattern structure and the second pattern structure. An oxidizing treatment step is performed to the spacers having a width gradually increased from tops of the spacers. A pattern defined with the spacers is transferred into the substrate after the oxidizing treatment step.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 28, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Lin Chen, An-Chi Liu, Kun-Yuan Liao, Cheng-Pu Chiu
  • Publication number: 20180166441
    Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.
    Type: Application
    Filed: November 28, 2017
    Publication date: June 14, 2018
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Hsiang-Hung Peng, Wei-Hao Huang, Ching-Wen Hung, Chih-Sen Huang
  • Patent number: 9985123
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Wei-Hao Huang
  • Publication number: 20180109225
    Abstract: A voltage controlled oscillator (“VCO”) circuit is disclosed. The VCO includes a switch module comprising a first transistor and a second transistor; a first LC-tank module, the first LC-tank module is operatively connected between the drain of the first transistor and the drain of the second transistor; and a second LC-tank module, the second LC-tank module is operatively connected between the gate of the first transistor and the gate of the second transistor, the source of the first transistor and the source of the second transistor are operatively connected.
    Type: Application
    Filed: October 19, 2016
    Publication date: April 19, 2018
    Inventors: Jun-De JIN, Ying-Ta Lu, Hsien-Yuan Liao