Patents by Inventor Yuan-Ping Tseng
Yuan-Ping Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7140101Abstract: A method for fabricating an anisotropic conductive substrate is disclosed. A back holder has metal pins on a surface thereof. A liquid compound is formed on the surface of the back holder with metal pins. The liquid compound is pressed to deform the metal pins into electrodes in the liquid compound. The thickness between upper surface and lower surface of the liquid compound is between 25 ?m and 250 ?m. The electrodes have upper ends and lower ends exposed from upper surface and lower surface of the liquid compound to provide electrical contact of anisotropic conduction.Type: GrantFiled: September 29, 2003Date of Patent: November 28, 2006Assignees: ChipMOS Technologies (Bermuda) Ltd., ChipMOS Technologies Inc.Inventors: Shih-Jye Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Yao-Jung Lee
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Patent number: 7005054Abstract: A method to make probes of a probe card includes providing a blocking plate on an electroplating tank. The blocking plate has a plurality of openings according to the layout of contact pads on a probe head. There are bumps on the contact pads of the probe head. Continuous electroplating process can be executed after bumps (contact pads) contact electroplating solution in the electroplating tank through the openings of the blocking plate. By continuously moving the probe head according to the desired shape of probes, probes were formed by electroplating. These probes can be made into different shapes with good uniformity in elasticity and heights to increase the quality of electrical contact during wafer probing. Moreover, the process lead time and fabrication cost are saved.Type: GrantFiled: August 20, 2002Date of Patent: February 28, 2006Assignees: Chipmos Technologies (Bermuda) Ltd., Chipmos Technologies Inc.Inventors: S. J. Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Y. J. Lee
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Publication number: 20050066521Abstract: A method for fabricating an anisotropic conductive substrate is disclosed. A back holder has metal pins on a surface thereof. A liquid compound is formed on the surface of the back holder with metal pins. The liquid compound is pressed to deform the metal pins into electrodes in the liquid compound. The thickness between upper surface and lower surface of the liquid compound is between 25 ?m and 250 ?m. The electrodes have upper ends and lower ends exposed from upper surface and lower surface of the liquid compound to provide electrical contact of anisotropic conduction.Type: ApplicationFiled: September 29, 2003Publication date: March 31, 2005Inventors: S. Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Y. Lee
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Publication number: 20050070049Abstract: A method for fabricating wafer-level chip scale packages is disclosed. A plurality of sacrificial photoresists with supporting surfaces in strip or bump configuration are formed on a surface of a wafer. Then, a negative photoresist layer is covered on the sacrificial photoresists. The negative photoresist layer is patterned in order to form a plurality of dielectric supporting bars on supporting surfaces of the sacrificial photoresists. Thereafter, a plurality of metal bars are formed on the dielectric supporting bars. Then the sacrificial photoresists are removed in order to form a plurality of pin terminals of the wafer-level chip scale packages for elastically surface-mounting to substrate or printed circuit board.Type: ApplicationFiled: September 29, 2003Publication date: March 31, 2005Inventors: S. Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Y. Lee
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Patent number: 6853205Abstract: A probe card assembly is disclosed. The probe card assembly comprises a stiffener ring combining respectively with an upper printed circuit board and a lower printed circuit board. A plurality of coaxial transmitters are installed in the stiffener ring, and connect to the upper and lower printed circuit boards by cable connectors. The lower printed circuit board is assembled with a detachable probe head which comprises a silicon substrate with probing points and a probe head carrier. A downset is formed at the center of the probe head carrier. The standardized coaxial transmitters, printed circuit boards and probe heads are then assembled as a probe card assembly for testing all sorts of IC products.Type: GrantFiled: July 17, 2003Date of Patent: February 8, 2005Assignees: Chipmos Technologies (Bermuda) Ltd., Chipmos Technologies Inc.Inventors: Shih-Jye Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Yao-Jung Lee
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Publication number: 20050014308Abstract: A manufacturing process of memory module with direct die-attachment is provided to integrate the process of packaging, module assembling and testing. When a plurality of memory chips are singulated from a wafer, a determined amount of the memory chips are directly mounted to a module substrate, and electrically connected to gold fingers of the module substrate. The module substrate mounting the memory chips is loaded in a memory module tester. The memory chips are tested to verify their electrical performance by contacting the gold fingers, and then the bad ones are repaired or replaced before packaging the memory chips. The manufacturing process of memory module with direct die-attachment can reduce the investment of testers and also the cost of testing.Type: ApplicationFiled: July 17, 2003Publication date: January 20, 2005Inventors: Yuan-Ping Tseng, An-Hong Liu, Y. Lee
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Publication number: 20050012513Abstract: A probe card assembly is disclosed. The probe card assembly comprises a stiffener ring combining respectively with an upper printed circuit board and a lower printed circuit board. A plurality of coaxial transmitters are installed in the stiffener ring, and connect to the upper and lower printed circuit boards by cable connectors. The lower printed circuit board is assembled with a detachable probe head which comprises a silicon substrate with probing points and a probe head carrier. A downset is formed at the center of the probe head carrier. The standardized coaxial transmitters, printed circuit boards and probe heads are then assembled as a probe card assembly for testing all sorts of IC products.Type: ApplicationFiled: July 17, 2003Publication date: January 20, 2005Inventors: Shih-Jye Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Yao-Jung Lee
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Patent number: 6812720Abstract: A modularized probe card with coaxial transmitter is disclosed. At least a coaxial transmitter is modularized and installed between a first printed circuit board and a second printed circuit board. The coaxial transmitter has a first connector and a second connector correspondingly connecting two ends of each coaxial cable of the coaxial transmitter for electrically connecting corresponding in location to first printed circuit board and second printed circuit board. A probe head is bonded on second printed circuit board. The second connector of the coaxial transmitter is connected with the second printed circuit board in a plug-in and pull-away type.Type: GrantFiled: April 17, 2003Date of Patent: November 2, 2004Assignees: Chipmos Technologies (Bermuda) Ltd., Chipmos Technologies Inc.Inventors: Shih-Jye Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Yao-Jung Lee
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Publication number: 20040207420Abstract: A modularized probe card with coaxial transmitter is disclosed. At least a coaxial transmitter is modularized and installed between a first printed circuit board and a second printed circuit board. The coaxial transmitter has a first connector and a second connector correspondingly connecting two ends of each coaxial cable of the coaxial transmitter for electrically connecting corresponding in location to first printed circuit board and second printed circuit board. A probe head is bonded on second printed circuit board. The second connector of the coaxial transmitter is connected with the second printed circuit board in a plug-in and pull-away type.Type: ApplicationFiled: April 17, 2003Publication date: October 21, 2004Inventors: S. J. Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Y. J. Lee
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Patent number: 6781392Abstract: A modularized probe card comprising an interface board, a probe head and at least a compressible electrical connection device is disclosed. The compressible electrical connection device comprises an insulation layer with a plurality of circuits on one of its surface. Two ends of each circuit connect respectively to the first contacting pad and the second contacting pad which combine with elastic contact members. Each elastic contact member has a supporter combining with a conductive layer for electrical connections by pushing and compressing. While a probe head is modularized installed on an interface board, the elastic contact members of the compressible electrical connection device is elastically contacted and compressed the probe head and the interface board to acquire modularized electrical connection of the probe card.Type: GrantFiled: May 12, 2003Date of Patent: August 24, 2004Assignees: Chipmos Technologies Ltd., Chipmos Technologies Inc.Inventors: Shih-Jye Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Yao-Jung Lee
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Patent number: 6751760Abstract: A method and a system for performing memory repair analysis are provided. A merge circuit is connected between test storage device of semiconductor testing equipment and pre-analysis storage device of repair analysis apparatus. Prior to memory repair analysis process, data from a plurality of functional tests are merged as a functional test data with addresses of fail bits by the merge circuit, then stored in pre-analysis storage device for analyzing. Therefore, test time is reduced and test efficiency is improved.Type: GrantFiled: November 20, 2001Date of Patent: June 15, 2004Assignee: ChipMOS Technologies Inc.Inventors: Yuan-Ping Tseng, Vincent Wang, Linck Cheng, An-Hong Liu
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Publication number: 20040035706Abstract: A method to make probes of a probe card includes providing a blocking plate on an electroplating tank. The blocking plate has a plurality of openings according to the layout of contact pads on a probe head. There are bumps on the contact pads of probe head. Continuous electroplating process can be executed after bumps (contact pads) contact electroplating solution in the electroplating tank through the openings of the blocking plate. By continuously moving the probe head according to the desired shape of probes, probes were formed by electroplating. These probes can be made into different shapes with good uniformity in elasticity and heights to increase the quality of electrical contact during wafer probing. Moreover, the process lead time and fabrication cost are saved.Type: ApplicationFiled: August 20, 2002Publication date: February 26, 2004Applicant: ChipMOS Technologies (Bermuda) Ltd. and ChipMOS TECHNOLOGIES INC.Inventors: S. J. Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Y. J. Lee
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Patent number: 6686615Abstract: A flip chip type semiconductor device for reducing signal skew includes: a chip with bonding pads, and a plurality of bumping pads on the chip. Between each bonding pad and corresponding bumping pads is connected with a metal redistribution trace covered by a passivation layer. Each metal trace has an equal trace length for reducing signal skew.Type: GrantFiled: August 20, 2002Date of Patent: February 3, 2004Assignees: Chipmos Technologies (Bermuda) Ltd., Chipmos Technologies Inc.Inventors: S. J. Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Y. J. Lee
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Publication number: 20040012405Abstract: A probe card with full wafer contact configuration comprises a back plate and a plurality of modular multiplayer ceramic wiring boards coplanarly mounted on the back plate. The total size of the modular multilayer ceramic wiring boards is larger than that of a wafer under test in order to fully contact all the bonding pads of the wafer under test. The modular multilayer ceramic wiring boards can be manufactured separately according to various locations. Thus, the manufacturing cost is reduced and yield is improved and lead time is shortened.Type: ApplicationFiled: July 19, 2002Publication date: January 22, 2004Applicants: ChipMOS Technologies (Bermuda) Ltd., ChipMOS TECHNOLOGIES INC.Inventors: S. J. Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Y. J. Lee
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Patent number: 6621710Abstract: A modular probe card assembly comprises a silicon substrate with probes modularly assembled on a main board. At least a socket is installed around silicon substrate and electrically connects to probe needles by a flexible printed wiring film. A plurality of detachable coaxial wires electrically connect sockets with the main board for achieving variability of connecting paths during manufacturing. Thus, the probe card assembly has the effect of adjustable amendment and is suitable for high speed testing.Type: GrantFiled: July 19, 2002Date of Patent: September 16, 2003Assignees: ChipMOS Technologies (Bermuda) Ltd., ChipMOS Technologies Inc.Inventors: Shih-Jye Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Yao-Jung Lee
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Patent number: 6605480Abstract: A wafer level packaging process for making flip-chips and integrated circuits formed are proposed. The process comprises in turn, providing a wafer, forming a protective material, bumping the wafer, removing the protective material, probing the wafer, laser repairing, and dicing the wafer. The laser repairing step is after bumping step. The protective material such as photoresist or metal layer is filled into the depression portions above the fuses for temporary protection of the fuses during bumping.Type: GrantFiled: November 28, 2001Date of Patent: August 12, 2003Assignee: ChipMOS Technologies Inc.Inventors: An-Hong Liu, Yuan-Ping Tseng, Y. J. Lee
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Publication number: 20030101388Abstract: A system and a method for avoiding waiting repair analysis for a semiconductor testing equipment are disclosed. The semiconductor testing equipment directly executes next functional test after transferring previous test data regardless of if repair analysis is completed or not. A repair analysis apparatus has a pre-analysis storage device with a larger capacity than the test storage device of the semiconductor testing equipment for off-line repair analysis, so that the semiconductor test is efficiently improved.Type: ApplicationFiled: November 28, 2001Publication date: May 29, 2003Applicant: ChipMOS TECHNOLOGIES INC.Inventors: Yuan-Ping Tseng, Vincent Wang, Linck Cheng, An-Hong Liu
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Publication number: 20030098494Abstract: A wafer level packaging process for making flip-chips and integrated circuits formed are proposed. The process comprises in turn, providing a wafer, forming a protective material, bumping the wafer, removing the protective material, probing the wafer, laser repairing, and dicing the wafer. The laser repairing step is after bumping step. The protective material such as photoresist or metal layer is filled into the depression portions above the fuses for temporary protection of the fuses during bumping.Type: ApplicationFiled: November 28, 2001Publication date: May 29, 2003Applicant: ChipMOS TECHNOLOGIES INC.Inventors: An-Hong Liu, Yuan-Ping Tseng, Y.J. Lee
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Publication number: 20030097626Abstract: A method and a system for performing memory repair analysis are provided. A merge circuit is connected between test storage device of semiconductor testing equipment and pre-analysis storage device of repair analysis apparatus. Prior to memory repair analysis process, data from a plurality of functional tests are merged as a functional test data with addresses of fail bits by the merge circuit, then stored in pre-analysis storage device for analyzing. Therefore, test time is reduced and test efficiency is improved.Type: ApplicationFiled: November 20, 2001Publication date: May 22, 2003Applicant: chipMOS TECHNOLOGIES INC.Inventors: Yuan-Ping Tseng, Vincent Wang, Linck Cheng, An-Hong Liu
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Patent number: 6534853Abstract: A semiconductor wafer is disclosed for avoiding probed marks while testing. The wafer has a plurality of metal interconnects, each metal interconnect connecting underlying bonding pad, corresponding contact pad and test pad. Each contact pad being outer electrical connection terminal is connected in series by a metal interconnect between test pad and bonding pad, so that the section of the metal interconnect between bonding pad and contact pad enable be tested during probing the test pad. Furthermore, there is no probing mark on the contact pad.Type: GrantFiled: June 5, 2001Date of Patent: March 18, 2003Assignee: ChipMOS Technologies Inc.Inventors: An-Hong Liu, Yuan-Ping Tseng