Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: Systems and methodologies are described that effectuate or facilitate detecting a cell (serving or neighboring cell) in multichannel wireless communication environments. In accordance with various aspects set forth herein, systems and/or methods are provided that receive signals from multiple cells and identify candidate cells based at least in part on the received signals, compare signal metrics for each of the candidate cells, select signal metrics associated with each of the candidate cells, and compare signal metrics to identify proximate base stations located within a candidate cell.

Abstract: A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.

Abstract: A spacer structure includes a first substrate, an overcoat layer, first spacers, second spacers, and a second substrate. The first spacers are disposed in a first region, and the overcoat layer has a first thickness in the first region. The second spacers are disposed in a second region, and the overcoat layer has a second thickness in the second region. The first spacers and the second spacers have the same height, and the first thickness is greater than the second thickness. Accordingly, no gap exists between each of the first spacers and the second substrate; however, a gap exists between each or the second spacers and the second substrate.

Abstract: A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate layer. Afterwards, the shadow mask is used as a mask to form a source layer, an organic semiconductor layer and a drain layer. Thus, the process is simplified. Since no photolithography process is required, and therefore damage of the organic semiconductor layer is avoided and a vertical TFT with desired electrical characteristics may be obtained.

Abstract: A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate layer. Afterwards, the shadow mask is used as a mask to form a source layer, an organic semiconductor layer and a drain layer. Thus, the process is simplified. Since no photolithography process is required, and therefore damage of the organic semiconductor layer is avoided and a vertical TFT with desired electrical characteristics may be obtained.

Abstract: A projector apparatus has an electrically conductive housing that includes a lower housing part and an upper housing part coupled to the lower housing part for covering the lower housing part, an internal projector module mounted in the housing, a first grounding component provided between the internal projector module and the upper housing part so as to establish a first grounding path between the internal projector module and the housing, and a second grounding component provided between the internal projector module and the lower housing part so as to establish a second grounding path between the internal projector module and the housing.

Abstract: A spacer structure of a display panel includes a first substrate, a second substrate, a spacer, and a spacer pad. The spacer is disposed on a side of the first substrate facing the second substrate, and the spacer pad is disposed between the second substrate and the spacer. The spacer pad has a non-linear structure lodged in the spacer, and therefore restrains the spacer from moving with respect to the second substrate in the plane parallel to the surface of the second substrate.

Abstract: A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate layer. Afterwards, the shadow mask is used as a mask to form a source layer, an organic semiconductor layer and a drain layer. Thus, the process is simplified. Since no photolithography process is required, and therefore damage of the organic semiconductor layer is avoided and a vertical TFT with desired electrical characteristics may be obtained.

Abstract: A method for forming a lamp holder. The lamp holder is applied in a projection apparatus. First, the lamp holder comprising metal is provided. An insulating layer is formed on one surface of the lamp holder to insulate the lamp holder from another element of the projection apparatus.

Abstract: A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data registers are respectively connected to the two groups of the nonvolatile memory cells. The compare circuit is connected to the two groups of the data registers, for performing a comparison to generate a compare result.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.

Abstract: A read reference determining the logical value for results read from memory is adjusted during unstable power conditions.

Abstract: A read reference determining the logical value for results read from memory is adjusted during unstable power conditions.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and loading nonvolatile memory data and nonvolatile memory complementary data to a read data register and a read complementary data register, respectively. The nonvolatile memory data and the nonvolatile memory complementary data are compared with the read data register and the read complementary data register during the power on sequence, e.g., after initial power up or power on reset (POR). When the comparison determines a mismatch, the loading of the nonvolatile memory data and the nonvolatile memory complementary data to the read data register and the read complementary data register, respectively, is repeated.

Abstract: This invention provides a laser trimming method for tuning the frequency of a spiral resonator, and for improving the characteristics of a high temperature superconductor filter comprised of high temperature superconductor spiral resonators, by tuning the individual high temperature superconductor spiral resonators. This invention also provides a method for tuning the resonance frequency of a high temperature superconductor planar coil. This invention also provides a laser ablation process for creating high temperature superconductor circuit elements.

Abstract: A method for making a thin film transistor (TFT) is provided. A mask is first formed on the backside of a substrate, and is used to fabricate a gate, source, and drain of the transistor by backside exposure, such that the source and drain can be self-aligned with the gate pattern. In this way, an alignment shift due to expansion or contraction after performing a high temperature process on an insulating layer can be avoided. Further, since the backside mask previously formed on the substrate can be shifted with the expansion or contraction of the substrate, the process is simplified. Moreover, the source/drain can be accurately aligned with the gate, so that parasitic capacitance can be reduced and flickering of the panel can be avoided.

Abstract: A structure of a thin film transistor (TFT) is provided. A substrate has a first surface and a second surface opposite to each other, in which the first surface has a patterned mask layer. A patterned first electrode layer is disposed on the second surface of the substrate and has a gate portion and a capacitor electrode portion. A patterned second electrode layer is disposed on the second surface of the substrate and has a source and a drain, in which the patterned second electrode layer is self-aligned with the patterned first electrode layer by exposing the first surface of the substrate with the patterned mask layer as a mask. An insulating layer is disposed between the patterned first electrode layer and the patterned second electrode layer.