Abstract: A method for making a multi-chip package device includes: providing a lead frame unit having a plurality of lead frames, each of the lead frames having a base seat that has an upper surface and a bottom surface, and a plurality of leads; electrically attaching a transistor chip onto the base seat, the transistor chip having a plurality of electrode pads; attaching a circuit control chip to the base seat; covering the transistor chip with a main conducting part, and electrically connecting the main conducting part with at least one of the source electrode pads; electrically connecting the circuit control chip to another source electrode pad; encapsulating the transistor chip and the circuit control chip to expose a leg part; and bending the leg part that is exposed to form a planar conducting portion having a bottom surface coplanar with the bottom surface of the base seat.

Abstract: A multi-chip package device includes a lead frame, a transistor chip, a metallic frame, a circuit control chip, and an encapsulation layer. The lead frame has a base seat, and a plurality of leads. The transistor chip is disposed on the base seat, and includes a plurality of source electrode pads, a gate electrode and a drain electrode. The metallic frame has a main conducting part and a conducting leg having a first conducting section and a second conducting section. The circuit control chip is disposed on the base seat and electrically connected to the transistor chip and the leads. The encapsulation layer envelops the lead frame, the transistor chip, the main conducting part, the first conducting section, and the circuit control chip to expose the second conducting section of the conducting leg.

Abstract: A trench-gate field effect transistor includes a plurality of trenches, a plurality of gate electrode units, and a plurality of source electrode units. Each of the trenches has a first trench region, a second trench region having a width less than that of the first trench region, and a neck trench region extending between the first trench region and the second trench region. Each of the gate electrode units includes a pair of first gate electrode portions disposed in the first trench region, a pair of second gate electrode portions disposed in the neck trench region, and a third gate electrode portion disposed in the second trench region. Each of the source electrode units includes a first source electrode portion disposed between a pair of the first gate electrode portions, and a second source electrode portion connected to the first source electrode portion.

Abstract: A metal-oxide semiconductor module includes multiple metal-oxide semiconductor components separated from one another by at least one first trench. Each of the metal-oxide semiconductor components includes a heavily doped semiconductor layer which includes a drain region, an epitaxial layer which is formed with an indentation such that the drain region is partially exposed from the epitaxial layer, and a metallic patterned contact unit. The epitaxial layer also includes a source region and a gate region that are spaced-apart formed therein. The metallic patterned contact unit includes source, gate, and drain patterned contacts which are electrically connected to the source, gate, and drain regions, respectively. A light-emitting diode display device including the metal-oxide semiconductor module is also disclosed.

Abstract: A metal-oxide-semiconductor (MOS) device comprising a heavily doped substrate, an epitaxial layer, an open, a plurality of MOS units, and a metal pattern layer is provided. The epitaxial layer is formed on the heavily doped substrate. The open is defined in the epitaxial layer to expose the heavily doped substrate. The MOS units are formed on the epitaxial layer. The metal pattern layer comprises a source metal pattern, a gate metal pattern, and a drain metal pattern. The source metal pattern and the gate metal pattern are formed on the epitaxial layer. The drain metal pattern fills in the open and is extended from the heavily doped substrate upward to above the epitaxial layer.

Abstract: A metal-oxide semiconductor module includes multiple metal-oxide semiconductor components separated from one another by at least one first trench. Each of the metal-oxide semiconductor components includes a heavily doped semiconductor layer which includes a drain region, an epitaxial layer which is formed with an indentation such that the drain region is partially exposed from the epitaxial layer, and a metallic patterned contact unit. The epitaxial layer also includes a source region and a gate region that are spaced-apart formed therein. The metallic patterned contact unit includes source, gate, and drain patterned contacts which are electrically connected to the source, gate, and drain regions, respectively. A light-emitting diode display device including the metal-oxide semiconductor module is also disclosed.

Abstract: A metal-oxide-semiconductor (MOS) device comprising a heavily doped substrate, epitaxialan layer, an open, a plurality of MOS units, and a metal pattern layer is provided. The epitaxial layer is formed on the heavily doped substrate. The open is defined in the epitaxial layer to expose the heavily doped substrate. The MOS units are formed on the epitaxial layer. The metal pattern layer comprises a source metal pattern, a gate metal pattern, and a drain metal pattern. The source metal pattern and the gate metal pattern are formed on the epitaxial layer. The drain metal pattern fills in the open and is extended from the heavily doped substrate upward to above the epitaxial layer.

Abstract: A multi-trench MOSFET includes a drain region, a body region, first trenches, first gates, second trenches, second gates, and source regions. The body region is disposed on the drain region. The first trenches are disposed side by side and extend in a first direction. The first trenches pass through the body region to enter into the drain region. The first gates are disposed in the first trenches respectively. The second trenches are disposed side by side and extend in a second direction different from the first direction. The second trenches pass through the body region to enter into the drain region. The first trenches and the second trenches are connected to divide the body region into blocks. A width of the second trench is 1.5 to 4 times that of the first trench. The second gates are disposed in the second trenches respectively. The source regions are disposed in the body region and abut the first trenches and the second trenches.

Abstract: A termination structure of MOSFET and a fabricating method thereof are provided. The fabricating method includes: forming a doped zone on a semiconductor substrate; forming trench rings in the doped zone; forming a gate oxide layer in each trench ring; depositing a polycrystalline silicon above the gate oxide layer; carrying out a back etching process of the polycrystalline silicon to form two self-aligned island polycrystalline silicon zones on two side walls of each of the trench rings, the two island polycrystalline silicon zones being not contact with each other; forming an insulation oxide layer in each of the trench rings; and covering the doped zone with a metal layer, and laying out the metal layer to form a discontinuous metal layer.

Abstract: A power metal-oxide-semiconductor (MOS) device is provided. The power MOS device is formed on a semiconductor substrate and includes an active region and a breakdown generated region. The active region includes a plurality of P-type doping regions and a plurality of N-type doping region alternatively arrayed between a source electrode and a drain electrode, and also includes a plurality of gate structures for controlling the conductive state of the active region. The breakdown generated region includes at least one P-type doping region and at least one N-type doping region alternatively arrayed between a source electrode and a drain electrode, and the breakdown voltage of the breakdown generated region is smaller than that of the active region.

Abstract: A photo relay includes an illuminating unit, a photoelectric conversion IC, a first MOS IC and a second MOS IC. The illuminating unit receives an input signal to generate an illuminating signal. The photoelectric conversion IC receives the illuminating signal to generate a voltage control signal accordingly. The second MOS IC is reversely stacked on the first MOS IC, such that the source electrodes of the two MOS ICs are electrically connected, and the gate electrodes of the two MOS ICs are electrically connected through a gate connection structure for receiving the voltage control signal, and the drain electrodes of the two MOS ICs generate an output signal according to the received voltage control signal.

Abstract: A photo relay includes an illuminating unit, a photoelectric conversion IC, a first MOS IC and a second MOS IC. The illuminating unit receives an input signal to generate an illuminating signal. The photoelectric conversion IC receives the illuminating signal to generate a voltage control signal accordingly. The second MOS IC is reversely stacked on the first MOS IC, such that the source electrodes of the two MOS ICs are electrically connected, and the gate electrodes of the two MOS ICs are electrically connected through a gate connection structure for receiving the voltage control signal, and the drain electrodes of the two MOS ICs generate an output signal according to the received voltage control signal.

Abstract: A power semiconductor device of stripe cell geometry including a substrate, a plurality of striped power semiconductor units, and a guard ring structure is provided. The substrate has an active area and a termination area surrounding the active area defined thereon. The striped semiconductor unit includes a striped gate conductive structure. The striped semiconductor units are located in the active area. The guard ring structure is located in the termination area and includes at least a ring-shaped conductive structure surrounding the striped power semiconductor units. The ring-shaped conductive structure and the striped gate conductive structures are formed on the same conductive layer, and at least one of the striped gate conductive structures is separated from the nearby ring-shaped conductive structure and electrically connected to the nearby ring-shaped conductive structure through the gate metal pad.

Abstract: A power semiconductor device of stripe cell geometry including a substrate, a plurality of striped power semiconductor units, and a guard ring structure is provided. The substrate has an active area and a termination area surrounding the active area defined thereon. The striped semiconductor unit includes a striped gate conductive structure. The striped semiconductor units are located in the active area. The guard ring structure is located in the termination area and includes at least a ring-shaped conductive structure surrounding the striped power semiconductor units. The ring-shaped conductive structure and the striped gate conductive structures are formed on the same conductive layer, and at least one of the striped gate conductive structures is separated from the nearby ring-shaped conductive structure and electrically connected to the nearby ring-shaped conductive structure through the gate metal pad.

Abstract: A test device includes a base, a locating component installed on the base, a platform disposed on the base, an operating component, a driving component installed on the platform, at least one light emitting component, at least one sensing component and a control unit. The driving component is for driving the operating component. The at least one light emitting component is disposed on at least one track of the platform for emitting light. The at least one sensing component is for sensing the light emitted from the at least one light emitting component and reflected from the workpiece. The control unit determines whether to control the driving component to drive the operating component to move to the workpiece according a sensing result of the at least one sensing component sensing the light emitted from the at least one light emitting component and reflected from the workpiece.

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.

Abstract: A closed cell trenched power semiconductor structure is provided. The closed cell trenched power semiconductor structure has a substrate and cells. The cells are arranged on the substrate in an array. Every cell has a body and a trenched gate. The trenched gate surrounds the body. A side wall of the trenched gate facing body has a concave.

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode.

Abstract: A closed cell trenched power semiconductor structure is provided. The closed cell trenched power semiconductor structure has a substrate and cells. The cells are arranged on the substrate in an array. Every cell has a body and a trenched gate. The trenched gate surrounds the body. A side wall of the trenched gate facing body has a concave.

Abstract: A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.