Patents by Inventor Yuan Su

Yuan Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12292687
    Abstract: In a method of pattern formation information including a pattern size on a reticle is received. A width of an EUV radiation beam is adjusted in accordance with the information. The EUV radiation beam is scanned on the reticle. A photo resist layer is exposed with a reflected EUV radiation beam from the reticle. An increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width is greater when the width before adjustment is W1 compared to an increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width when the width before adjustment is W2 when W1>W2.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: May 6, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi Yang, Tsung-Hsun Lee, Jian-Yuan Su, Ching-Juinn Huang, Po-Chung Cheng
  • Publication number: 20250142940
    Abstract: A method for manufacturing a semiconductor device includes: forming a first fin portion and a second fin portion on a semiconductor substrate, the first fin portion and the second fin portion being spaced apart from each other; and forming a first gate dielectric layer and a second gate dielectric layer on the first fin portion and the second fin portion, respectively, the first gate dielectric layer having a first thickness, the second gate dielectric layer having a second thickness different from the first thickness.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 1, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chuan-Cheng TSOU, Po-Yuan SU, Sung-Hsin YANG, Jung-Chi JENG, Chen-Chieh CHIANG
  • Publication number: 20250140770
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a photonic integrated circuit chip and an electronic integrated circuit chip are disposed on opposite sides of an interposer respectively, and the photonic integrated circuit chip and the electronic integrated circuit chip can accomplish signal connection with each other via a plurality of conductive vias in the interposer directly, thereby reducing the power consumption and transmission delay of the signals transmitted between the circuits.
    Type: Application
    Filed: March 27, 2024
    Publication date: May 1, 2025
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Che-Yu LEE, Chi-Ching HO, Chao-Chiang PU, Yi-Min FU, Po-Yuan SU
  • Publication number: 20250087601
    Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Po-Yuan SU
  • Publication number: 20250079254
    Abstract: An electronic package is provided and includes: a thermally conductive chip; a circuit structure having a circuit layer; and an electronic component disposed between the circuit structure and the thermally conductive chip and electrically connected to the circuit layer, so as to dissipate the heat generated during the operation of the electronic component via the thermally conductive chip. A method of manufacturing the electronic package is further provided.
    Type: Application
    Filed: January 4, 2024
    Publication date: March 6, 2025
    Inventors: Po-Yuan SU, Chi-Ching HO, Chao-Chiang PU, Yi-Min FU, Che-Yu LEE
  • Patent number: 12240952
    Abstract: In one aspect, the disclosure relates to cooling films comprising a substrate and one or more cooling materials deposited on the substrate. The disclosed cooling films can be used to prepare the disclosed cooling masterbatch materials. The disclosed cooling masterbatch materials can be used to prepare disclosed cooling yarns. The one or more cooling materials deposited on the substrate of a disclosed cooling film, dispersed in a disclosed cooling masterbatch material, or in disclosed cooling yarn are nano-sized particles. In still further aspects, the present disclosure pertains to a fabric comprising a disclosed cooling yarn. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present disclosure.
    Type: Grant
    Filed: December 11, 2021
    Date of Patent: March 4, 2025
    Assignee: BRRR! Inc.
    Inventors: Cheng-Shang Tsao, Hung-Yuan Su
  • Patent number: 12237152
    Abstract: A two-dimensional electronic component includes a substrate; an artificial two-dimensional (2D) material disposed on the substrate; and a first metallic electrode disposed on the artificial 2D material. The artificial 2D material includes a layered atomic structure including a middle atomic layer, a lower atomic layer disposed on a lower surface of the middle atomic layer, and an upper atomic layer disposed on an upper surface of the middle atomic layer respectively. The upper atomic layer and the first metallic electrode are attracted together at a junction therebetween by metallic bonding.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: February 25, 2025
    Assignee: NATIONAL CENTRAL UNIVERSITY
    Inventors: Ching-Yuan Su, En Yi Liao
  • Publication number: 20250040209
    Abstract: An artificial double-layer two-dimensional material includes a first layered atomic structure and a second layered atomic structure. The first layered atomic structure includes a first middle atomic layer, a first lower atomic layer, and a first upper atomic layer. The first lower and the first upper atomic layers are disposed on lower and upper surfaces of the first middle atomic layer respectively. The second layered atomic structure includes a second middle atomic layer, a second lower atomic layer, and a second upper atomic layer. The second lower and the second upper atomic layers are disposed on lower and upper surfaces of the second middle atomic layer respectively. The first middle atomic layer and the second middle atomic layer are two-dimensional planar atomic structures formed of transition metals. The first lower and the first upper atomic layers are 2D planar atomic structures formed of heterogeneous atom.
    Type: Application
    Filed: October 14, 2024
    Publication date: January 30, 2025
    Inventors: CHING-YUAN SU, REN-KUEI LIAO
  • Publication number: 20250022958
    Abstract: A semiconductor device includes a substrate having fins and trenches in between the fins, a plurality of insulators, a first metal layer, an insulating layer, a second metal layer and an interlayer dielectric. The insulators are disposed within the trenches of the substrate. The first metal layer is disposed on the plurality of insulators and across the fins. The insulating layer is disposed on the first metal layer over the plurality of insulators and across the fins. The second metal layer is disposed on the insulating layer over the plurality of insulators and across the fins. The interlayer dielectric is disposed on the insulators and covering the first metal layer, the insulating layer and the second metal layer.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 16, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-You TAI, Ling-Sung Wang, Chen-Chieh Chiang, Jung-Chi Jeng, Po-Yuan Su, Tsung Jing Wu
  • Patent number: 12199047
    Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 14, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Po-Yuan Su
  • Patent number: 12180062
    Abstract: A microelectromechanical apparatus includes a base and a thin film including a stationary part disposed on the base, a peripheral part, a central part surrounded by the peripheral part, and a first and second elastic part. The first elastic part is connected to the stationary part and the peripheral part. The second elastic part is connected to the peripheral part and the central part. When low frequency signal is input to a first electrode of the first elastic part, the peripheral part and the and the central part respectively vibrate with a first and second low-frequency amplitudes. When high-frequency signal is input to a second electrode of the second elastic part, the peripheral part and the central part respectively vibrate with a first and second high-frequency amplitudes. A difference between the first and second low-frequency amplitudes is smaller than a difference between the first and second high-frequency amplitudes.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: December 31, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jen-Chieh Li, Chao-Ta Huang, Chung-Yuan Su, RueiHung Kao
  • Publication number: 20240419082
    Abstract: A method includes: protecting a mask of a mask assembly by a frame thereon during translating the mask assembly to a position associated with a region of a substrate, the frame having height less than a focal plane associated with a selected particle size; directing extreme ultraviolet (EUV) radiation toward the mask; reflecting radiation carrying a pattern of the mask toward the mask layer; forming a feature of a semiconductor device in a layer underlying the mask layer according to the pattern.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: Ming-Hsin CHEN, Zi-Wen CHEN, Chi YANG, Yao-Tang LIN, Jian-Yuan SU
  • Publication number: 20240385509
    Abstract: A method includes: determining whether a first pellicle is to be inspected for inner particles; and in response to the first pellicle being to be inspected: forming a mask layer on a substrate; forming a defocused light path by shifting a mask assembly; exposing the mask layer by defocused light having a focal plane separated from the first pellicle by a distance; taking an image of the substrate; determining whether a threshold value is exceeded by analyzing the image; in response to the threshold value being exceeded, replacing the first pellicle with a second pellicle; and in response to the threshold value not being exceeded, processing production wafers using the first pellicle.
    Type: Application
    Filed: May 19, 2023
    Publication date: November 21, 2024
    Inventors: Chi YANG, Yao-Tang LIN, Zi-Wen CHEN, Jian-Yuan SU
  • Patent number: 12138958
    Abstract: A hub structure includes a tubular body defining a hollow cavity. The tubular body includes a first surface and a second surface, the first surface defining a first groove extending along an axial direction of the tubular body. The first groove is defined by an inner sidewall surrounding the hollow cavity, an outer sidewall spaced from and configured to face the inner sidewall, and a bottom surface coupling the inner sidewall and the outer sidewall.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: November 12, 2024
    Assignee: GIANT MANUFACTURING CO., LTD.
    Inventor: Hui-Yuan Su
  • Publication number: 20240363545
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a full-panel wafer is provided and includes a plurality of electronic bodies arranged in an array at intervals, a plurality of trenches are formed across the electronic bodies along a first direction on the full-panel wafer, so that the trenches on a single electronic body are arranged parallel to each other at interval and along a second direction perpendicular to the first direction. Then, in a singulation process, any trench can be selected for cutting to obtain a plurality of electronic elements of a required size. Finally, each of the electronic elements is disposed on a packaging region of a carrier structure, so that each of the electronic elements is electrically connected to at least a portion of electrical contact pads in the packaging region.
    Type: Application
    Filed: July 14, 2023
    Publication date: October 31, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Che-Yu LEE, Chi-Ching HO, Chao-Chiang PU, Yi-Min FU, Po-Yuan SU
  • Publication number: 20240353763
    Abstract: A reticle includes a border section surrounding a pattern section, and gas openings arranged in and passing through the border section. The gas openings are coupled to a gas supply. Each gas opening extends in a first direction inclined to and forming an angle with a reticle center axis that extends perpendicularly away from a front surface of the reticle, and is configured to blow a pressurized gas in the first direction away from the front surface to create an air wall adjacent to and surrounding the front surface, thereby advantageously preventing particles from falling on the front surface of the reticle.
    Type: Application
    Filed: April 21, 2023
    Publication date: October 24, 2024
    Inventors: Yao-Tang LIN, Tzu-Wen CHEN, Jian-Yuan SU, Ming-Hsin CHEN
  • Publication number: 20240303052
    Abstract: Systems and methods for application/data dependency identification, visualization, and/or management.
    Type: Application
    Filed: March 9, 2023
    Publication date: September 12, 2024
    Inventors: Yushen C. Michelsen, Chunlei Li, Subash Maharjan, Yuan Su, Andrew Lin, David Rollins
  • Publication number: 20240297279
    Abstract: A light source assembly is provided, including a substrate; a light-emitting element disposed on the substrate; and an optical film disposed on the light-emitting element. A diffuser layer is disposed between the optical film and the light-emitting element, wherein a haze of the diffuser layer is greater than 85%, a distance between the diffuser layer and the light-emitting element is in a range from 0 mm to 10 mm, and a thickness of the light-emitting element is less than the distance.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: Chia-Lun CHEN, Shih-Chang HUANG, Ming-Hui CHU, Chih-Chang CHEN, Kai-Hsien HSIUNG, Hui-Chi WANG, Wun-Yuan SU
  • Publication number: 20240264389
    Abstract: An electronic package and the manufacturing method thereof are provided, in which a photonic element and an electronic element are embedded in an encapsulation layer, and the photonic element has an external contact area exposed from the encapsulation layer, such that signals of the electronic element can be directly transmitted to an optical fiber via the external contact area of the photonic element to achieve the purpose of photoelectric integration.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 8, 2024
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Che-Yu LEE, Po-Yuan SU
  • Patent number: 12025588
    Abstract: A microelectromechanical sensing apparatus with calibration function comprises a microelectromechanical sensor and an IC chip. The microelectromechanical sensor comprises a proof mass, a movable driving electrode and a movable sensing electrode disposed on the proof mass, and a stationary driving electrode and stationary sensing electrode disposed on a substrate, wherein the sensing electrodes output a sensing signal when the proof mass vibrates.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: July 2, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chung-Yuan Su, Chin-Fu Kuo, Liang-Ying Liu, Chao-Ta Huang