Patents by Inventor Yuan Su

Yuan Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961912
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Publication number: 20240120391
    Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region disposed under a well portion, a second source/drain region disposed adjacent the first source/drain region, a dielectric material disposed between the first and second source/drain regions, and a conductive contact having a first portion disposed under the first source/drain region and a second portion disposed adjacent the first source/drain region. The second portion is disposed in the dielectric material. The structure further includes a conductive feature disposed in the dielectric material, and the conductive feature is electrically connected to the conductive contact. The conductive feature has a top surface that is substantially coplanar with a top surface of the well portion.
    Type: Application
    Filed: January 19, 2023
    Publication date: April 11, 2024
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Chih-Hao WANG
  • Patent number: 11955515
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
  • Patent number: 11942530
    Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Chih-Hao Wang
  • Publication number: 20240093142
    Abstract: The present invention relates to the fields of microorgan-isms, feed, food and ecological restoration, in particular to a strain for degrading deoxynivalenol (DON) and the use thereof. The strain has the deposit number CCTCC No. M 2020565. The strain can grow by means of taking the toxic compound DON as a sole carbon source, and convert the DON into chemical components for itself. The reaction process is irreversible, the reaction conditions are moderate, and secondary pollu-tion cannot be caused. The strain provided in the present invention can be used for preparing a biological detoxification preparation for DON. The strain provided in the present invention can be used for degrading DON in feed and food raw materials, primary processing products, deep processing products and related processing byproducts. The strain provided in the present invention can be applied to various ecosystems such as soil or bodies of water polluted by DON to achieve the purposes of DON degradation and ecological restoration.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 21, 2024
    Inventors: Huiying LUO, Honghai ZHANG, Bin YAO, Huoqing HUANG, Yaru WANG, Yingguo BAI, Xiaoyun SU, Yuan WANG, Tao TU, Jie ZHANG, Huimin YU, Xing QIN, Xiaolu WANG
  • Publication number: 20240096701
    Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.
    Type: Application
    Filed: May 17, 2023
    Publication date: March 21, 2024
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Ching-Wei TSAI, Shang-Wen CHANG, Yi-Hsun CHIU, Chih-Hao WANG
  • Publication number: 20240096996
    Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Lo-Heng Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11935957
    Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Publication number: 20240083137
    Abstract: Embodiments of this application provide a composite structure including a substrate layer and a functional layer disposed on a surface of at least one side of the substrate layer. The substrate layer includes a first support member and a second support member that are disposed side by side and a bendable connecting member connected to and disposed between the first support member and the second support member. A material of the first support member and the second support member includes a hard rubber fiber composite material, and the functional layer includes one or more of an electrically conductive layer, a thermally conductive layer, or an impact-resistant layer.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Yuan QIN, Yangyang LI, Chun ZOU, Weiwei YAO, Nanjian SUN, Taimeng CHEN, Zhaoliang SU
  • Patent number: 11923889
    Abstract: Various embodiments include methods and systems having detection apparatus operable to cancel or reduce leakage signal originating from a source signal being generated and transmitted from a transmitter. A leakage cancellation signal can be generated digitally, converted to an analog signal, and then subtracted in the analog domain from a received signal to provide a leakage-reduced signal for use in detection and analysis of objects. A digital cancellation signal may be generated by generating a cancellation signal in the frequency domain and converting it to the time domain. Optionally, an estimate of a residual leakage signal can be generated and applied to reduce residual leakage remaining in the leakage-reduced signal. Additional apparatus, systems, and methods can be implemented in a variety of applications.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: March 5, 2024
    Assignee: Futurewei Technologies, Inc.
    Inventors: Ricky Lap Kei Cheung, Luzhou Xu, Lixi Wu, Hsing Kuo Lo, Yuan Su
  • Patent number: 11912919
    Abstract: This present disclosure provides a core-shell quantum dot, a preparation method thereof, and a light-emitting device containing the same. The core of the core-shell quantum dot is CdSeXS(1-X), and the quantum dot shells include a first shell and a second shell, the first shell being selected from one or more of ZnSe, ZnSeYS(1-Y) and Cd(Z)Zn(1-Z)S, the second shell covering the first shell being one of Cd(Z)Zn(1-Z)S and ZnS, the maximum emission peak of the core-shell quantum dot is less than or equal to 480 nm, 0<X<1, 0<Y<1, 0<Z<1. The CdSeXS(1-X) core has a smaller bandgap and a shallower HOMO energy level, making hole injection easier.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: February 27, 2024
    Assignee: Najing Technology Corporation Limited
    Inventors: Baozhong Hu, Guangxu Li, Yanhong Mao, Yuan Gao, Yehua Su
  • Publication number: 20240061332
    Abstract: A method of patterning a semiconductor layer includes the following steps. The semiconductor layer is formed on a substrate. A photoresist layer is formed on the semiconductor layer. The photoresist layer is patterned to form an opening exposing an exposed region of the semiconductor layer. The exposed region of the semiconductor layer is dissolved with a solution to pattern the semiconductor layer, in which the solution includes a first organic solvent and a second organic solvent. The solubility of the semiconductor layer in the first organic solvent is greater than 1 mg/mL, and the solubility of the semiconductor layer in the second organic solvent is less than or equal to 1 mg/mL.
    Type: Application
    Filed: November 15, 2022
    Publication date: February 22, 2024
    Inventors: Yi-Ming CHANG, Chia-Hua TSAI, Hsin-Yuan SU
  • Publication number: 20230391965
    Abstract: In one aspect, the disclosure relates to cooling films comprising a substrate and one or more cooling materials deposited on the substrate. The disclosed cooling films can be used to prepare the disclosed cooling masterbatch materials. The disclosed cooling masterbatch materials can be used to prepare disclosed cooling yarns. The one or more cooling materials deposited on the substrate of a disclosed cooling film, dispersed in a disclosed cooling masterbatch material, or in disclosed cooling yarn are nano-sized particles. In still further aspects, the present disclosure pertains to a fabric comprising a disclosed cooling yarn. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present disclosure.
    Type: Application
    Filed: December 11, 2021
    Publication date: December 7, 2023
    Inventors: Cheng-Shang TSAO, Hung-Yuan SU
  • Publication number: 20230368064
    Abstract: Methods, systems, and apparatus for gradient-based quantum assisted Hamiltonian learning. In one aspect, a method includes obtaining, by a classical processor, multiple experimental data points, wherein each experimental data point is generated according to a Hamiltonian comprising parameters with unknown values; learning, by the classical processor, values of the parameters, comprising iteratively adjusting, by the classical processor and until predetermined completion criteria are met, estimated values of the parameters to minimize a cost function, wherein the cost function is dependent on the multiple experimental data points and at each iteration derivatives of the cost function with respect to respective estimated values of the parameters for the previous iteration are computed using a quantum computer.
    Type: Application
    Filed: September 2, 2022
    Publication date: November 16, 2023
    Inventors: Thomas Eugene O'Brien, Vadim Smelyanskiy, Lev loffe, Yuan Su, Ryan Babbush
  • Publication number: 20230367221
    Abstract: In a method of pattern formation information including a pattern size on a reticle is received. A width of an EUV radiation beam is adjusted in accordance with the information. The EUV radiation beam is scanned on the reticle. A photo resist layer is exposed with a reflected EUV radiation beam from the reticle. An increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width is greater when the width before adjustment is W1 compared to an increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width when the width before adjustment is W2 when W1>W2.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Chi YANG, Tsung-Hsun Lee, Jian-Yuan Su, Ching-Juinn Huang, Po-Chung Cheng
  • Patent number: 11796917
    Abstract: In a method of pattern formation information including a pattern size on a reticle is received. A width of an EUV radiation beam is adjusted in accordance with the information. The EUV radiation beam is scanned on the reticle. A photo resist layer is exposed with a reflected EUV radiation beam from the reticle. An increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width is greater when the width before adjustment is W1 compared to an increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width when the width before adjustment is W2 when W1>W2.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi Yang, Tsung-Hsun Lee, Jian-Yuan Su, Ching-Juinn Huang, Po-Chung Cheng
  • Publication number: 20230331611
    Abstract: A method of visible-light photocatalysis combined with ClO2 oxidation for high efficient removal of organic pollutants in the wastewater, includes that i) the pH of the organic wastewater is adjusted to a constant value; the visible light photocatalysts are added to wastewater with full stirring to reach the adsorption equilibrium; (ii) turning on the Xenon lamp and adjust the distance between the light source and the liquid surface; chlorite is added to the system to reach a concentration and the reaction remained at a constant temperature with adequate stirring to achieve the degradation of organic pollutants.
    Type: Application
    Filed: August 19, 2020
    Publication date: October 19, 2023
    Inventors: Qian LI, Ruidian SU, Yuan SU
  • Patent number: 11791847
    Abstract: Embodiments of this disclosure provide a system and method for wireless communication and wireless sensing in a low-cost common transceiver structure. In particular, the common transceiver structure may have a common digital-to-analog converter (DAC) configured to convert a digital wireless communication signal and a digital wireless sensing signal into an analog wireless communication signal and an analog wireless sensing signal, respectively. The common transceiver may also have a common transmitting antenna configured to transmit the analog wireless communication signal and the analog wireless sensing signal.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: October 17, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Luzhou Xu, Ricky Lap Kei Cheung, Hsing Kuo Lo, Yan Li, Yuan Su
  • Publication number: 20230212431
    Abstract: The present invention relates to an ethylene-vinyl alcohol copolymer composition, a single-layer film and a multilayer structure containing the same. Said ethylene-vinyl alcohol copolymer composition includes an ethylene-vinyl alcohol copolymer, an antioxidant, and a fluorine-containing compound; and the ratio of the antioxidant content to the fluorine content is 0.5 to 65. Thereby, the film containing said ethylene-vinyl alcohol copolymer composition not only has good heat resistance, but also can avoid the situation that a large number of gels are generated during the preparation process.
    Type: Application
    Filed: June 30, 2022
    Publication date: July 6, 2023
    Inventors: Shih Yuan Su, Hou Hsi Wu
  • Patent number: D1018907
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: March 19, 2024
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Yun-Chien Lee, Yi-Ching Hsu, Pei-Yi Lin, Yu-Hung Su, Sheng-Yuan Huang, Chun-Fu Lin