Abstract: A method includes forming first and second gate stacks over a substrate. Each of the first and second gate stacks includes a tunneling dielectric layer, a floating gate over the tunneling dielectric layer, a middle dielectric layer over the floating gate, and a control gate over the middle dielectric layer. A conductive layer is formed over the first and second gate stacks. The conductive layer is etched to form a erase gate between the first and second gate stacks. Etching the conductive layer is performed such that a top surface of the erase gate is not higher than a top surface of the control gate and such that the top surface of the erase gate is at least partially curved inwards.

Abstract: A method for forming an inductor structure is provided. The method includes forming a first metal layer over a substrate and forming an oxide layer over the first metal layer. The method also includes forming a magnetic material in and over the oxide layer, and the magnetic material includes a first portion and a second portion, the first portion is directly over the oxide layer, and the second portion is in the oxide layer. The method further includes removing the first portion and a portion of the second portion of the magnetic material to form a magnetic layer, such that a recession is between the magnetic layer and the oxide layer. The method further includes forming a dielectric layer over the magnetic layer, wherein the recession is filled with the dielectric layer.

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

Abstract: In some methods, a contact is formed over a substrate, and a bottom electrode layer is formed over the contact. A first dielectric layer is formed to cover a peripheral portion of the bottom electrode layer but not a central portion of the bottom electrode layer. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer includes a central dielectric region that contacts the central portion of the bottom electrode layer, and a peripheral dielectric region over the peripheral portion of the bottom electrode. A step dielectric region connects the central and peripheral dielectric regions. A top electrode layer is formed over the second dielectric layer. The top electrode layer includes a central top electrode region, a peripheral top electrode region, and a step top electrode region directly above the central dielectric region, the peripheral dielectric region, and the step dielectric region, respectively.

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.

Abstract: A method for forming an inductor structure is provided. The method includes forming a first metal layer over a substrate and forming an oxide layer over the first metal layer. The method also includes forming a magnetic material in and over the oxide layer, and the magnetic material includes a first portion and a second portion, the first portion is directly over the oxide layer, and the second portion is in the oxide layer. The method further includes removing the first portion and a portion of the second portion of the magnetic material to form a magnetic layer, such that a recession is between the magnetic layer and the oxide layer. The method further includes forming a dielectric layer over the magnetic layer, wherein the recession is filled with the dielectric layer.

Abstract: A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure also includes a top electrode formed over the MTJ cell; and a first sidewall spacer layer formed on a top surface of the MTJ cell and an outer sidewall surface of the top electrode.

Abstract: A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure includes a top electrode formed over the MTJ cell and a passivation layer surrounding the top electrode. The passivation layer has a recessed portion that is lower than a top surface of the top electrode. The semiconductor memory structure further includes a cap layer formed on the top electrode and the passivation layer, wherein the cap layer is formed in the recessed portion.

Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: A memory cell with a hard mask and a sidewall spacer of different material is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A hard mask disposed over the top electrode. A sidewall spacer extends upwardly along sidewalls of the switching dielectric, the top electrode, and the hard mask. The hard mask and the sidewall spacer have different etch selectivity. A method for manufacturing the memory cell is also provided.

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.

Abstract: The present disclosure provides a semiconductor structure, including a memory region and a logic region adjacent to the memory region. The memory region includes a first Nth metal line, a first stop layer being disposed over a magnetic tunneling junction (MTJ) over the first Nth metal line, and a first (N+1)th metal via being disposed over the MTJ and surrounded by the first stop layer, the first (N+1)th metal via having a first height. The logic region includes a second Nth metal line, a second stop layer being disposed over an (N+1)th metal line, and a second (N+1)th metal via over the (N+1)th metal line and having a second height. N is an integer greater than or equal to 1 and the first height is greater than the second height. A method of manufacturing the semiconductor structure is also disclosed.

Abstract: A memory device includes a bottom electrode, a resistance switching element, a top electrode, a spacer and a conductive feature. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching electrode. The spacer abuts the resistance switching element. The conductive feature is over the top electrode. The spacer is at least partially between the conductive feature and the top electrode.

Abstract: A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure includes a top electrode formed over the MTJ cell and a passivation layer surrounding the top electrode. The passivation layer has a recessed portion that is lower than a top surface of the top electrode. The semiconductor memory structure further includes a cap layer formed on the top electrode and the passivation layer, wherein the cap layer is formed in the recessed portion.

Abstract: A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure also includes a top electrode formed over the MTJ cell; and a first sidewall spacer layer formed on a top surface of the MTJ cell and an outer sidewall surface of the top electrode.

Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.