Patents by Inventor Yuan Tsai
Yuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240194534Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.Type: ApplicationFiled: February 26, 2024Publication date: June 13, 2024Inventors: Ya-Yi Tsai, Yi-Hsuan Hsiao, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
-
Publication number: 20240194711Abstract: An optical device includes a photoelectric conversion layer, an anti-reflection layer, an underlying layer, a bottom meta layer, and a top meta layer. The photoelectric conversion layer includes a plurality of photodiodes. The anti-reflection layer is disposed on the photoelectric conversion layer. The underlying layer is disposed on the anti-reflection layer. The bottom meta layer is disposed on the underlying layer and includes a plurality of bottom meta units and a filling between the bottom meta units, in which the filling is continuously extend from the underlying layer, and a material of the filling is the same as a material of the underlying layer. The top meta layer is disposed above the bottom meta layer and includes a plurality of top meta units and a plurality of air recesses, in which the plurality of air recesses are respectively disposed between two adjacent top meta units.Type: ApplicationFiled: December 12, 2022Publication date: June 13, 2024Inventors: Chun-Yuan WANG, Po-Hsiang WANG, Han-Lin WU, Hung-Jen TSAI
-
Publication number: 20240192456Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: ApplicationFiled: February 26, 2024Publication date: June 13, 2024Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
-
Patent number: 12009281Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.Type: GrantFiled: January 28, 2022Date of Patent: June 11, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Chen, Hao-Yi Tsai, Kuo-Lung Pan, Tin-Hao Kuo, Po-Yuan Teng, Chi-Hui Lai
-
Patent number: 11998894Abstract: A composite solid base catalyst, a manufacturing method thereof and a manufacturing method of glycidol are provided. The composite solid base catalyst includes an aluminum carrier and a plurality of calcium particles. The plurality of calcium particles are supported by the aluminum carrier. Beta basic sites of the composite solid base catalyst are 0.58 mmol/g-3.89 mmol/g.Type: GrantFiled: June 14, 2022Date of Patent: June 4, 2024Assignees: NATIONAL TSING HUA UNIVERSITY, Chang Chun Plastics Co., Ltd., Chang Chun Petrochemical Co., LTD., DAIREN CHEMICAL CORP.Inventors: De-Hao Tsai, Yung-Tin Pan, Che-Ming Yang, Ching-Yuan Chang, Ding-Huei Tsai, Chien-Fu Huang, Yi-Ta Tsai
-
Patent number: 12002799Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.Type: GrantFiled: July 25, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hua Yu, Hung-Yi Kuo, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Yuan Yu, Ming Hung Tseng
-
Patent number: 12002776Abstract: An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mth row extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The second pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nth conductive lines.Type: GrantFiled: July 12, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jung-Chou Tsai, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu, Yi-Kan Cheng
-
Patent number: 12001308Abstract: A creating method of a classification model about a hard disk efficiency problem comprising: by an analyzing device, performing: obtaining a plurality of pieces of measurement data of a plurality of hard disk devices each of which comprises a plurality of values of a plurality of vibration parameters; binarizing the plurality of pieces of measurement data based on a plurality of preset conditions respectively corresponding to the plurality of vibration parameters; and obtaining the classification model about the hard disk efficiency problem based on the plurality of pieces of binarized measurement data and a decision tree algorithm.Type: GrantFiled: June 15, 2022Date of Patent: June 4, 2024Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATIONInventors: Yi-Ju Liao, Jen-Yuan Chang, Po-Hsiu Chen, Hsieh-Liang Tsai
-
Patent number: 12002715Abstract: A method includes forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; etching the dummy gate material using a first etching process to form a recess between the first fin and the second fin, wherein a sacrificial material is formed on sidewalls of the recess during the first etching process; filling the recess with an insulation material; removing the dummy gate material and the sacrificial material using a second etching process; and forming a first replacement gate over the first fin and a second replacement gate over the second fin, wherein the first replacement gate is separated from the second replacement gate by the insulation material.Type: GrantFiled: July 8, 2020Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ya-Yi Tsai, Wei-Ting Guo, I-Wei Yang, Shu-Yuan Ku
-
Publication number: 20240178152Abstract: The present disclosure relates to a method for forming a mark, a packaging method for a semiconductor device, and a semiconductor device having the mark, wherein the marking material is a polymer compound and the light transmittance of the marking material is less than 50%, which is suitable for forming the mark on the semiconductor device by laser sintering, and the marking material is sintered to make the resin cross-link and cure to form a cured product. In addition, in one embodiment, the cured product formed by the marking material can be used as a deflector to guide the flow of the underfill and control the flow rate of underfill, so as to effectively solve the problem of uneven flow rate of the underfill.Type: ApplicationFiled: January 20, 2023Publication date: May 30, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei CHEN, Po-Yuan TENG, Chiahung LIU, HAO-YI TSAI
-
Publication number: 20240178102Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.Type: ApplicationFiled: April 21, 2023Publication date: May 30, 2024Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
-
Publication number: 20240178150Abstract: A semiconductor device package structure is provided, including a redistribution structure, a first semiconductor device, a second semiconductor device, a bridge die, a first conductive bump, and a second conductive bump bumps, a third conductive bumps, and a first solder material. The first semiconductor device is disposed on a first side of the redistribution structure, the second semiconductor device and the bridge die are disposed on a second side opposite to the first side. The first conductive bump is disposed on the first semiconductor device, the second conductive bump is disposed on the second side of the redistribution structure and the third conductive bump is disposed on the second semiconductor device. The first solder material is electrically connected between the second conductive bump and the third conductive bump, and the redistribution structure is electrically connected between the first conductive bump and the second conductive bump.Type: ApplicationFiled: January 19, 2023Publication date: May 30, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzuan-Horng LIU, Hao-Yi TSAI, Tsung-Yuan YU
-
Patent number: 11996195Abstract: A training data processing method and an electronic device are provided. The method includes: obtaining medical history data including at least one first disease suffered by a user; setting a plurality of disease types according to a target disease; setting a time interval; obtaining at least one second disease in the time interval from the medical history data; performing a pre-processing operation on the second disease according to the disease types to obtain processed data; and inputting the processed data to a neural network to train the neural network.Type: GrantFiled: April 9, 2020Date of Patent: May 28, 2024Assignees: Acer Incorporated, National Yang-Ming UniversityInventors: Pei-Jung Chen, Tsung-Hsien Tsai, Liang-Kung Chen, Li-Ning Peng, Fei-Yuan Hsiao, Shih-Tsung Huang
-
Patent number: 11996472Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.Type: GrantFiled: February 9, 2023Date of Patent: May 28, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ya-Yi Tsai, Chi-Hsiang Chang, Shih-Yao Lin, Tzu-Chung Wang, Shu-Yuan Ku
-
Publication number: 20240169757Abstract: An electronic device includes a light source and an optical sensor. The light source emits a light having a maximum light intensity at a first wavelength A. The optical sensor has a maximum response value at a second wavelength B, and receives a reflected portion of the light that is reflected by an object. The integral value of the light intensity of the light from the wavelength 380 nm to the first wavelength A is I1. The integral value of the light intensity of the light from the first wavelength A to the wavelength 780 nm is I2. The first wavelength A, the second wavelength B, the integral value I1, and the integral value I2 satisfy the following equation: (B?A)*(I2?I1)>0.Type: ApplicationFiled: October 18, 2023Publication date: May 23, 2024Inventors: Jia-Yuan CHEN, Tsung-Han TSAI
-
Publication number: 20240170381Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.Type: ApplicationFiled: February 1, 2024Publication date: May 23, 2024Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan CAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
-
Publication number: 20240170299Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Inventors: KUN-JU LI, ANG CHAN, HSIN-JUNG LIU, WEI-XIN GAO, JHIH-YUAN CHEN, CHUN-HAN CHEN, ZONG-SIAN WU, CHAU-CHUNG HOU, I-MING LAI, FU-SHOU TSAI
-
Patent number: 11990341Abstract: A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.Type: GrantFiled: August 9, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Uei Jang, Ya-Yi Tsai, Ryan Chia-Jen Chen, An Chyi Wei, Shu-Yuan Ku
-
Patent number: 11990381Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.Type: GrantFiled: November 14, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
-
Publication number: 20240162051Abstract: Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.Type: ApplicationFiled: April 27, 2023Publication date: May 16, 2024Inventors: Kuo-Ming WU, Hau-Yi HSIAO, Kai-Yun YANG, Che Wei YANG, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI