Patents by Inventor Yuan Tsai

Yuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178150
    Abstract: A semiconductor device package structure is provided, including a redistribution structure, a first semiconductor device, a second semiconductor device, a bridge die, a first conductive bump, and a second conductive bump bumps, a third conductive bumps, and a first solder material. The first semiconductor device is disposed on a first side of the redistribution structure, the second semiconductor device and the bridge die are disposed on a second side opposite to the first side. The first conductive bump is disposed on the first semiconductor device, the second conductive bump is disposed on the second side of the redistribution structure and the third conductive bump is disposed on the second semiconductor device. The first solder material is electrically connected between the second conductive bump and the third conductive bump, and the redistribution structure is electrically connected between the first conductive bump and the second conductive bump.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 30, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzuan-Horng LIU, Hao-Yi TSAI, Tsung-Yuan YU
  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
  • Publication number: 20240178152
    Abstract: The present disclosure relates to a method for forming a mark, a packaging method for a semiconductor device, and a semiconductor device having the mark, wherein the marking material is a polymer compound and the light transmittance of the marking material is less than 50%, which is suitable for forming the mark on the semiconductor device by laser sintering, and the marking material is sintered to make the resin cross-link and cure to form a cured product. In addition, in one embodiment, the cured product formed by the marking material can be used as a deflector to guide the flow of the underfill and control the flow rate of underfill, so as to effectively solve the problem of uneven flow rate of the underfill.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei CHEN, Po-Yuan TENG, Chiahung LIU, HAO-YI TSAI
  • Patent number: 11996195
    Abstract: A training data processing method and an electronic device are provided. The method includes: obtaining medical history data including at least one first disease suffered by a user; setting a plurality of disease types according to a target disease; setting a time interval; obtaining at least one second disease in the time interval from the medical history data; performing a pre-processing operation on the second disease according to the disease types to obtain processed data; and inputting the processed data to a neural network to train the neural network.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: May 28, 2024
    Assignees: Acer Incorporated, National Yang-Ming University
    Inventors: Pei-Jung Chen, Tsung-Hsien Tsai, Liang-Kung Chen, Li-Ning Peng, Fei-Yuan Hsiao, Shih-Tsung Huang
  • Patent number: 11996472
    Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.
    Type: Grant
    Filed: February 9, 2023
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ya-Yi Tsai, Chi-Hsiang Chang, Shih-Yao Lin, Tzu-Chung Wang, Shu-Yuan Ku
  • Publication number: 20240170381
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan CAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20240169757
    Abstract: An electronic device includes a light source and an optical sensor. The light source emits a light having a maximum light intensity at a first wavelength A. The optical sensor has a maximum response value at a second wavelength B, and receives a reflected portion of the light that is reflected by an object. The integral value of the light intensity of the light from the wavelength 380 nm to the first wavelength A is I1. The integral value of the light intensity of the light from the first wavelength A to the wavelength 780 nm is I2. The first wavelength A, the second wavelength B, the integral value I1, and the integral value I2 satisfy the following equation: (B?A)*(I2?I1)>0.
    Type: Application
    Filed: October 18, 2023
    Publication date: May 23, 2024
    Inventors: Jia-Yuan CHEN, Tsung-Han TSAI
  • Publication number: 20240170299
    Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Inventors: KUN-JU LI, ANG CHAN, HSIN-JUNG LIU, WEI-XIN GAO, JHIH-YUAN CHEN, CHUN-HAN CHEN, ZONG-SIAN WU, CHAU-CHUNG HOU, I-MING LAI, FU-SHOU TSAI
  • Patent number: 11990341
    Abstract: A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Uei Jang, Ya-Yi Tsai, Ryan Chia-Jen Chen, An Chyi Wei, Shu-Yuan Ku
  • Patent number: 11990381
    Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
  • Publication number: 20240162051
    Abstract: Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.
    Type: Application
    Filed: April 27, 2023
    Publication date: May 16, 2024
    Inventors: Kuo-Ming WU, Hau-Yi HSIAO, Kai-Yun YANG, Che Wei YANG, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
  • Publication number: 20240156440
    Abstract: A method of reconstructing transcranial images using a dual-mode ultrasonic phased array includes steps of: controlling channels to emit energy toward an intracranial target point of a patient; respectively generating backscattered radiofrequency (RF) data by using the channels to receive backscattered energy reflected from the intracranial target; and reconstructing an acoustic distribution image based on those backscattered RF data in real-time. Compared with Pre-Treatment Ray Tracing Method, the present invention can display intracranial pressure distribution in real-time; compared with MR Thermometry, the present invention can be applied to low-energy applications without temperature change; and compared with Passive Cavitation Imaging, the present invention can stably present acoustic distribution images without relying on microbubbles.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 16, 2024
    Inventors: HAO-LI LIU, HSIANG-CHING LIN, ZHEN-YUAN LIAO, HSIANG-YANG MA, CHIH-HUNG TSAI, CHUN-HAO CHEN
  • Publication number: 20240161660
    Abstract: A display device and a housing of the display device are provided. The housing of the display device includes a reflective cover. The reflective cover has a plurality of segments formed on a front side of the reflective cover and a plurality of segment structures correspondingly formed on a rear side of the reflective cover. At least one of the segment structures has a notch formed thereat. Positions of the notches of the at least two adjacent ones of the segment structures are not opposite to each other.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 16, 2024
    Inventors: CHENG-YAN HSIEH, SHIH-YUAN KUO, Jie-Ting Tsai
  • Patent number: 11984261
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Publication number: 20240155664
    Abstract: A method of logical channel prioritization and a device thereof are provided.
    Type: Application
    Filed: October 19, 2023
    Publication date: May 9, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Tzu-Jane Tsai, Chun-Yuan Chiu
  • Publication number: 20240153827
    Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 9, 2024
    Inventors: Shih-Yao Lin, Chih-Han Lin, Shu-Uei Jang, Ya-Yi Tsai, Shu-Yuan Ku
  • Publication number: 20240155421
    Abstract: A method and a user equipment for reporting a remaining delay budget information are provided. The method includes: receiving a radio resource control configuration, wherein the radio resource control configuration indicates the user equipment to report the remaining delay budget information of a logical channel or a logical channel group through a status report message; determining whether a triggering condition is met, wherein the triggering condition is associated with a threshold of remaining delay budget; and in response to the triggering condition being met, transmitting the status report message including the remaining delay budget information, wherein the remaining delay budget information indicates at least one remaining delay budget and at least one associated buffer size.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 9, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chun-Yuan Chiu, Tzu-Jane Tsai, Fang-Ching Ren
  • Publication number: 20240153943
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 9, 2024
    Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
  • Patent number: 11970241
    Abstract: A brake handle structure for a bicycle contains: at least one body, at least one rotatory arm, at least one brake lever, at least one angle signal sensor, and at least one power failure sensor. The at least one body includes a connection portion, an extension, and an engagement portion. The at least one rotatory arm includes a pulling segment, a coupling orifice, and a receiving orifice. The at least one brake lever includes a fixing segment connected with at least one electromagnetic clutch which includes a bolt attracted electromagnetically by the at least one electromagnetic clutch after conducting a power, and a defining orifice is defined adjacent to the at least one electromagnetic clutch. The at least one angle signal sensor is configured to sense and send a rotating angle of the rotatable column. The at least one power failure sensor has a movable sensing head.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: April 30, 2024
    Assignee: Joy Industrial (Shenzhen) Co., Ltd.
    Inventor: Chien-Yuan Tsai
  • Patent number: 11971624
    Abstract: A display device includes a first display unit emitting a green light having a first output spectrum corresponding to a highest gray level of the display device and a second display unit emitting a blue light having a second output spectrum corresponding to the highest gray level of the display device. The first output spectrum has a main wave with a first peak. The second output spectrum has a main wave with a second peak and a sub wave with a sub peak. The second peak corresponds to a main wavelength, the sub peak corresponds to a sub wavelength, and the main wavelength is less than the sub wavelength. An intensity of the second peak is greater than an intensity of the sub peak and an intensity of the first peak.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: April 30, 2024
    Assignee: InnoLux Corporation
    Inventors: Hsiao-Lang Lin, Jia-Yuan Chen, Jui-Jen Yueh, Kuan-Feng Lee, Tsung-Han Tsai