Abstract: A power system includes an energy storage system having a rechargeable energy storage element and a converter connected to the rechargeable energy storage element and configured to connect to a bus so that the energy storage system is connected in parallel with a load and a main power supply system. The energy storage system may cooperate with the main power supply system to supply power to the load with each of the energy storage system and the main power supply system configured as a voltage source with a corresponding droop function. The system may include a control circuit configured to monitor a voltage of the bus and control the converter to either charge or discharge the rechargeable energy storage element based on the voltage of the bus.

Abstract: Provided are an integrated circuit (IC) and a method of forming the same. The IC includes a substrate; a conductive layer, disposed on the substrate; a barrier layer, disposed on the conductive layer; an etching stop layer, covering a sidewall of the barrier layer and extending on a first portion of a top surface of the barrier layer; and at least one capacitor structure, disposed on a second portion of the top surface of the barrier layer.

Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

Abstract: A connection pairing method is used to establish a wireless transmission connection between a first electronic device and a second electronic device. Each electronic device is capable of operating in a wireless network mode and/or a network hotspot mode. The connection pairing method includes disabling the network hotspot mode of the first electronic device, connecting the first electronic device to the hotspot of the second electronic device, and transmitting the hotspot connection information of the first electronic device to the second electronic device; upon receiving the hotspot connection information of the first electronic device, setting the second electronic device to wireless network mode and enabling the network hotspot mode of the first electronic device; and establishing a hotspot connection between the second electronic device and the first electronic device based on the hotspot connection information.

Abstract: Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.

Abstract: A power system comprises an energy storage system including a rechargeable energy storage element and a converter connected to the rechargeable energy storage element and configured to connect to a bus so that the energy storage system is connected in parallel with a load and a main power supply system. The energy storage system cooperates with the main power supply system to supply power to the load. The power system may include a control circuit configured to monitor a voltage of the bus and control the converter to either charge or discharge the rechargeable energy storage element based on the voltage of the bus. The control circuit may also monitor a status of a state of charge (SOC) of the rechargeable energy storage element and a system load condition.

Abstract: The present invention relates to a light emitting diode (LED) which comprises multiple point-like conductive electrodes, a dielectric layer, and an epitaxial composite layer. The dielectric layer is disposed around each point-like conductive electrode, and the epitaxial composite layer is disposed both on the point-like conductive electrodes and the dielectric layer. Each point-like conductive electrode includes an ohmic-contact metal layer and a carbon-doped gallium arsenide epitaxial layer. The carbon-doped gallium arsenide epitaxial layer is disposed on the ohmic-contact metal layer and electrically connected to the epitaxial composite layer.

Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.

Abstract: The present invention relates to a light-emitting diode (LED) which comprises multiple point-like transparent conductive electrodes, a dielectric layer, and an epitaxial composite layer. The dielectric layer is disposed around each point-like transparent conductive electrode. The epitaxial composite layer comprises a carbon-doped gallium arsenide epitaxial layer. The carbon-doped gallium arsenide epitaxial layer is disposed both on each point-like transparent conductive electrode and the dielectric layer and electrically connected to each point-like transparent conductive electrode.

Abstract: A method for manufacturing a display device is provided. The method includes providing an array module having at least one first alignment mark. The method also includes providing a light-emitting module having at least one second alignment mark. The method further includes aligning the light-emitting module and the array module by the at least one first alignment mark and the at least one second alignment mark. In addition, the method includes bonding the light-emitting module onto the array module.

Abstract: An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: The present invention relates to a light-emitting diode (LED) which includes an epitaxial composite layer, a dielectric layer, a transparent conductive layer, and a metal layer. Specifically, the epitaxial composite layer is disposed on the dielectric layer, the dielectric layer is disposed on the transparent conductive layer, and the transparent conductive layer is disposed on the metal layer. Moreover, an outer edge of the transparent conductive layer is covered by the metal layer.

Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: An integrated circuit (IC) device includes an interlayer dielectric (ILD), first and second tower structures embedded in the ILD, and first and second ring regions including portions of the ILD that correspondingly extend around the first and second tower structures. Each of the first and second tower structures includes a plurality of conductive patterns in a plurality of metal layers, and a plurality of vias between the plurality of metal layers along a thickness direction of the IC device. The plurality of conductive patterns and the plurality of vias are coupled to each other to form the corresponding first or second tower structure. The first ring region extends around the first tower structure, without extending around the second tower structure.

Abstract: An electronic device includes a light source and an optical sensor. The light source emits a light having a maximum light intensity at a first wavelength A. The optical sensor has a maximum response value at a second wavelength B, and receives a reflected portion of the light that is reflected by an object. The integral value of the light intensity of the light from the wavelength 380 nm to the first wavelength A is I1. The integral value of the light intensity of the light from the first wavelength A to the wavelength 780 nm is I2. The first wavelength A, the second wavelength B, the integral value I1, and the integral value I2 satisfy the following equation: (B-A)*(I2-I1)>0.

Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.

Abstract: An operation image positioning method is disclosed. A point-cloud camera captures a point-cloud image of first and second positioning marks respectively fixed on a treated portion and an X-ray imaging machine. The first and second positioning marks within the point-cloud image are recognized to compute a first conversion module between the point-cloud camera and the treated portion and a second conversion module between the point-cloud camera and the X-ray imaging machine, thereby computing a third conversion module between the treated portion and the X-ray imaging machine. An image positioning camera captures a positioning image of the first positioning mark. The first positioning mark within the positioning image is recognized to compute a fourth conversion module between the image positioning camera and the treated portion. A fifth conversion module between the image positioning camera and the X-ray imaging machine is computed according to the third and fourth conversion modules.