Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

Abstract: A computer system (such as a controller) that selects channels and/or channel widths for use during communication in a shared band of frequencies is described. During operation, the computer system may receive, associated with access points in a region (such as a zone), information specifying unavailable channels associated with the shared band of frequencies, where the unavailable channels are currently used by the access points. For example, the information may be included in access-point status reports from the access points. Then, based at least in part on the unavailable channels, the computer system may determine the channels and/or the channel widths for use by the access points during communication in the shared band of frequencies in the region. Next, the computer system may provide, addressed to the access points, second information specifying the determined channels and/or the channel width.

Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.

Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

Abstract: The present disclosure provides a method of analyzing a semiconductor device. The method includes providing a first transistor, a second transistor disposed adjacent to the first transistor, and a gate electrode common to the first transistor and the second transistor; connecting a power-supply voltage (Vdd) to the gate electrode to turn on the first transistor, determining a first threshold voltage (Vth) based on the power-supply voltage; switching the power-supply voltage to a ground voltage (Vss); connecting the ground voltage to the gate electrode to turn on the second transistor; and determining a second threshold voltage based on the ground voltage.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over and passing through the insulating layer. The conductive pillar is formed in one piece, the conductive pillar is in direct contact with the first conductive line, and a first sidewall of the first conductive line extends across a second sidewall of the conductive pillar in a top view of the first conductive line and the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface and a bottom protruding portion protruding from the lower surface, the bottom protruding portion passes through the insulating layer over the first conductive line, the bottom protruding portion is in direct contact with the first conductive line, and a first linewidth of a first portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Abstract: During operation, a computer system may receive, from an electronic device, a VNI assignment message, where the VNI assignment message specifies a range of VNIs for VXLANs and one or more associated data planes. In response, the computer system may compute whether one or more VNIs in the range of VNIs are available. For example, the computer system may communicate with the VXLANs and/or may perform a look-up operation in a data structure in memory with information about VNIs (such as available VNIs and/or unavailable VNIs). When the one or more VNIs are unavailable, the computer system may provide, to the electronic device, an error message. Alternatively, when the one or more VNIs in the range of VNIs are available, the computer system may: modify the one or more data planes that implement the VXLANs with the range of VNIs; and provide, to the electronic device, an acknowledgment message.

Abstract: The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch, a second switch, and a third switch. The first switch has a first node coupled to a first device-under-test and a second node coupled to a first signal supply node. The second switch has a first node coupled to the second DUT and a second node coupled to the first signal supply node. The third switch has a first node directly coupled to the first DUT and the second DUT. The third switch has a second node coupled to a second signal supply node. The third switch selectively couples both of the first DUT and the second DUT to the second signal supply node.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface and a bottom protruding portion protruding from the lower surface, the bottom protruding portion passes through the insulating layer over the first conductive line, the bottom protruding portion is in direct contact with the first conductive line, and a first linewidth of a first portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.

Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

Abstract: The present disclosure provides a method of analyzing a semiconductor device. The method includes providing a first transistor, a second transistor disposed adjacent to the first transistor, and a gate electrode common to the first transistor and the second transistor; connecting a power-supply voltage (Vdd) to the gate electrode to turn on the first transistor, determining a first threshold voltage (Vth) based on the power-supply voltage; switching the power-supply voltage to a ground voltage (Vss); connecting the ground voltage to the gate electrode to turn on the second transistor; and determining a second threshold voltage based on the ground voltage.

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.

Abstract: A method, a test line and a system for detecting defects on a semiconductor wafer are presented. The method includes measuring a current-voltage (IV) curve of a plurality of metal oxide semiconductor (MOS) transistors which are connected in series in a test key; comparing the measured IV curve with a reference curve to obtain a first drain current drop in a linear region and a second drain current drop in a saturation region; and determining whether at least one of the MOS transistor among the MOS transistors of the test key is defected according to at least one of the first drain current drop and the second drain current drop.

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.

Abstract: A method, a test line and a system for detecting defects on a semiconductor wafer are presented. The method includes measuring a current-voltage (IV) curve of a plurality of metal oxide semiconductor (MOS) transistors which are connected in series in a test key; comparing the measured IV curve with a reference curve to obtain a first drain current drop in a linear region and a second drain current drop in a saturation region; and determining whether at least one of the MOS transistor among the MOS transistors of the test key is defected according to at least one of the first drain current drop and the second drain current drop.

Abstract: One or more probe cards, wafer testers, and techniques for testing a semiconductor arrangement are provided. Testline arrangements are formed within scribe lines of a semiconductor wafer, in multiple directions, such as an x-direction and a y-direction. A wafer tester is configured to concurrently test the semiconductor arrangement in multiple directions using a multidirectional probe arrangement of a probe card. In some embodiments, a first pin arrangement of the multidirectional probe arrangement is mated with a first testline arrangement in a first direction, and a second pin arrangement of the multidirectional probe arrangement is mated with a second testline arrangement in a second direction. The wafer tester concurrently tests the semiconductor arrangement in multiple directions, such as in the first direction and the second direction, through the pin arrangements mated with the testline arrangements.