Abstract: One or more probe cards, wafer testers, and techniques for testing a semiconductor arrangement are provided. Testline arrangements are formed within scribe lines of a semiconductor wafer, in multiple directions, such as an x-direction and a y-direction. A wafer tester is configured to concurrently test the semiconductor arrangement in multiple directions using a multidirectional probe arrangement of a probe card. In some embodiments, a first pin arrangement of the multidirectional probe arrangement is mated with a first testline arrangement in a first direction, and a second pin arrangement of the multidirectional probe arrangement is mated with a second testline arrangement in a second direction. The wafer tester concurrently tests the semiconductor arrangement in multiple directions, such as in the first direction and the second direction, through the pin arrangements mated with the testline arrangements.

Abstract: A method of measuring a parameter of a device in a circuit includes providing a device under test (DUT). The DUT includes a metal oxide semiconductor (MOS) transistor having a gate, a source, and a drain coupled to a first voltage supply node. The method further includes coupling a constant current source to the source of the transistor, coupling an operational amplifier to the transistor, and measuring a parameter of the transistor.

Abstract: A method of measuring a parameter of a device in a circuit includes providing a device under test (DUT). The DUT includes a metal oxide semiconductor (MOS) transistor having a gate, a source, and a drain coupled to a first voltage supply node. The method further includes coupling a constant current source to the source of the transistor, coupling an operational amplifier to the transistor, and measuring a parameter of the transistor.