Patents by Inventor Yuan-Yin Lo
Yuan-Yin Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12074137Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: February 9, 2023Date of Patent: August 27, 2024Assignee: Industrial Technology Research InstituteInventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Chao-Jung Chen, Tzu-Hsuan Ni, Shin-Yi Huang, Yuan-Yin Lo
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Publication number: 20230187409Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.Type: ApplicationFiled: February 9, 2023Publication date: June 15, 2023Applicant: Industrial Technology Research InstituteInventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Chao-Jung Chen, Tzu-Hsuan Ni, Shin-Yi Huang, Yuan-Yin Lo
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Patent number: 11646270Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.Type: GrantFiled: October 8, 2020Date of Patent: May 9, 2023Assignee: Industrial Technology Research InstituteInventors: Ang-Ying Lin, Yu-Min Lin, Shin-Yi Huang, Sheng-Tsai Wu, Yuan-Yin Lo, Tzu-Hsuan Ni, Chao-Jung Chen
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Patent number: 11587905Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: October 8, 2020Date of Patent: February 21, 2023Assignee: Industrial Technology Research InstituteInventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Chao-Jung Chen, Tzu-Hsuan Ni, Shin-Yi Huang, Yuan-Yin Lo
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Patent number: 11569217Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.Type: GrantFiled: January 5, 2022Date of Patent: January 31, 2023Assignee: Industrial Technology Research InstituteInventors: Sheng-Tsai Wu, Yu-Min Lin, Yuan-Yin Lo, Ang-Ying Lin, Tzu-Hsuan Ni, Chao-Jung Chen, Shin-Yi Huang
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Patent number: 11424190Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.Type: GrantFiled: August 27, 2020Date of Patent: August 23, 2022Assignee: Industrial Technology Research InstituteInventors: Chao-Jung Chen, Yu-Min Lin, Sheng-Tsai Wu, Shin-Yi Huang, Ang-Ying Lin, Tzu-Hsuan Ni, Yuan-Yin Lo
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Publication number: 20220130812Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.Type: ApplicationFiled: January 5, 2022Publication date: April 28, 2022Applicant: Industrial Technology Research InstituteInventors: Sheng-Tsai Wu, Yu-Min Lin, Yuan-Yin Lo, Ang-Ying Lin, Tzu-Hsuan Ni, Chao-Jung Chen, Shin-Yi Huang
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Patent number: 11251174Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.Type: GrantFiled: May 27, 2020Date of Patent: February 15, 2022Assignee: Industrial Technology Research InstituteInventors: Sheng-Tsai Wu, Yu-Min Lin, Yuan-Yin Lo, Ang-Ying Lin, Tzu-Hsuan Ni, Chao-Jung Chen, Shin-Yi Huang
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Publication number: 20210118860Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.Type: ApplicationFiled: May 27, 2020Publication date: April 22, 2021Applicant: Industrial Technology Research InstituteInventors: Sheng-Tsai Wu, Yu-Min Lin, Yuan-Yin Lo, Ang-Ying Lin, Tzu-Hsuan Ni, Chao-Jung Chen, Shin-Yi Huang
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Publication number: 20210111126Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.Type: ApplicationFiled: October 8, 2020Publication date: April 15, 2021Applicant: Industrial Technology Research InstituteInventors: Ang-Ying Lin, Yu-Min Lin, Shin-Yi Huang, Sheng-Tsai Wu, Yuan-Yin Lo, Tzu-Hsuan Ni, Chao-Jung Chen
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Publication number: 20210111153Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.Type: ApplicationFiled: October 8, 2020Publication date: April 15, 2021Applicant: Industrial Technology Research InstituteInventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Chao-Jung Chen, Tzu-Hsuan Ni, Shin-Yi Huang, Yuan-Yin Lo
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Publication number: 20210111125Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.Type: ApplicationFiled: August 27, 2020Publication date: April 15, 2021Applicant: Industrial Technology Research InstituteInventors: Chao-Jung Chen, Yu-Min Lin, Sheng-Tsai Wu, Shin-Yi Huang, Ang-Ying Lin, Tzu-Hsuan Ni, Yuan-Yin Lo
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Patent number: D976852Type: GrantFiled: June 18, 2020Date of Patent: January 31, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Sheng-Tsai Wu, Hsin-Han Lin, Yuan-Yin Lo, Kuo-Shu Kao, Tai-Jyun Yu, Han-Lin Wu, Yen-Ting Lin