Patents by Inventor Yuan-Yin Lo

Yuan-Yin Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12074137
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: February 9, 2023
    Date of Patent: August 27, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Chao-Jung Chen, Tzu-Hsuan Ni, Shin-Yi Huang, Yuan-Yin Lo
  • Publication number: 20230187409
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: February 9, 2023
    Publication date: June 15, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Chao-Jung Chen, Tzu-Hsuan Ni, Shin-Yi Huang, Yuan-Yin Lo
  • Patent number: 11646270
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: May 9, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Ang-Ying Lin, Yu-Min Lin, Shin-Yi Huang, Sheng-Tsai Wu, Yuan-Yin Lo, Tzu-Hsuan Ni, Chao-Jung Chen
  • Patent number: 11587905
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: February 21, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Chao-Jung Chen, Tzu-Hsuan Ni, Shin-Yi Huang, Yuan-Yin Lo
  • Patent number: 11569217
    Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: January 31, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Sheng-Tsai Wu, Yu-Min Lin, Yuan-Yin Lo, Ang-Ying Lin, Tzu-Hsuan Ni, Chao-Jung Chen, Shin-Yi Huang
  • Patent number: 11424190
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: August 23, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Jung Chen, Yu-Min Lin, Sheng-Tsai Wu, Shin-Yi Huang, Ang-Ying Lin, Tzu-Hsuan Ni, Yuan-Yin Lo
  • Publication number: 20220130812
    Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.
    Type: Application
    Filed: January 5, 2022
    Publication date: April 28, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Sheng-Tsai Wu, Yu-Min Lin, Yuan-Yin Lo, Ang-Ying Lin, Tzu-Hsuan Ni, Chao-Jung Chen, Shin-Yi Huang
  • Patent number: 11251174
    Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: February 15, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Sheng-Tsai Wu, Yu-Min Lin, Yuan-Yin Lo, Ang-Ying Lin, Tzu-Hsuan Ni, Chao-Jung Chen, Shin-Yi Huang
  • Publication number: 20210118860
    Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.
    Type: Application
    Filed: May 27, 2020
    Publication date: April 22, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Sheng-Tsai Wu, Yu-Min Lin, Yuan-Yin Lo, Ang-Ying Lin, Tzu-Hsuan Ni, Chao-Jung Chen, Shin-Yi Huang
  • Publication number: 20210111126
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 15, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Ang-Ying Lin, Yu-Min Lin, Shin-Yi Huang, Sheng-Tsai Wu, Yuan-Yin Lo, Tzu-Hsuan Ni, Chao-Jung Chen
  • Publication number: 20210111153
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 15, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Chao-Jung Chen, Tzu-Hsuan Ni, Shin-Yi Huang, Yuan-Yin Lo
  • Publication number: 20210111125
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.
    Type: Application
    Filed: August 27, 2020
    Publication date: April 15, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Chao-Jung Chen, Yu-Min Lin, Sheng-Tsai Wu, Shin-Yi Huang, Ang-Ying Lin, Tzu-Hsuan Ni, Yuan-Yin Lo
  • Patent number: D976852
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: January 31, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Tsai Wu, Hsin-Han Lin, Yuan-Yin Lo, Kuo-Shu Kao, Tai-Jyun Yu, Han-Lin Wu, Yen-Ting Lin