Abstract: A common electrode of a display panel is disclosed. The common electrode is located at a side of a gate driving device of the display panel, and the common electrode includes multiple main trunk electrodes arranged sequentially along a row direction, along the row direction, from a side closed to the gate driving device to a side away from the gate driving electrode, in adjacent two main trunk electrodes, a common voltage on a previous main trunk electrode is less than or equal to a common voltage on a next main trunk electrode, and a common voltage of a first main trunk electrode is less than a common voltage on a last main trunk electrode. The present invention can reduce the uneven display caused by RC delay on the transmission of the scanning signal.

Abstract: An array substrate is disclosed. The array substrate includes a semiconductor active layer, a gate insulation layer, a first metal layer, an interlayer dielectric layer, a second metal layer, a planarization layer and a passivation layer sequentially disposed on a base substrate; wherein the array substrate is provided with a row driving unit, including a capacitor structure; wherein the capacitor structure includes a first capacitive plate formed in the semiconductor active layer, a second capacitive plate formed in the first metal layer and a third capacitive plate formed in the second metal layer; and wherein projections of the first capacitive plate and the second capacitive plate on the base substrate are partially overlapped, projections the second capacitive plate and the third capacitive plate on the base substrate are partially overlapped and the third capacitive plate is electrically connected to the first capacitive plate through a first via hole.

Abstract: A common electrode of a display panel is disclosed. The common electrode is located at a side of a gate driving device of the display panel, and the common electrode includes multiple main trunk electrodes arranged sequentially along a row direction, along the row direction, from a side closed to the gate driving device to a side away from the gate driving electrode, in adjacent two main trunk electrodes, a common voltage on a previous main trunk electrode is less than or equal to a common voltage on a next main trunk electrode, and a common voltage of a first main trunk electrode is less than a common voltage on a last main trunk electrode. The present invention can reduce the uneven display caused by RC delay on the transmission of the scanning signal.

Abstract: An array substrate is disclosed. The array substrate includes a semiconductor active layer, a gate insulation layer, a first metal layer, an interlayer dielectric layer, a second metal layer, a planarization layer and a passivation layer sequentially disposed on a base substrate; wherein the array substrate is provided with a row driving unit, including a capacitor structure; wherein the capacitor structure includes a first capacitive plate formed in the semiconductor active layer, a second capacitive plate formed in the first metal layer and a third capacitive plate formed in the second metal layer; and wherein projections of the first capacitive plate and the second capacitive plate on the base substrate are partially overlapped, projections the second capacitive plate and the third capacitive plate on the base substrate are partially overlapped and the third capacitive plate is electrically connected to the first capacitive plate through a first via hole.

Abstract: A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield can be increased to effectively improve productivity. Heavy and light ion doping can be simultaneously achieved with one single doping operation so that manufacturing cost can be reduced. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to contact the two ends of the active layer thereby effectively reducing contact resistance and improving product yield. Also provided is a TFT substrate manufactured with the method.

Abstract: An electrostatic protection circuit of a display panel includes a first P-type thin film transistor having a gate connected to a high potential electrostatic output line and a drain connected to a high potential electrostatic output line, a second P-type thin film transistor having a gate connected to a high potential electrostatic output line and a drain connected to a source of the first P-type thin film transistor, and a source connected to the electrostatic signal input line; a first N-type thin film transistor having a gate connected to the low potential electrostatic output line, and a drain connected to the low potential electrostatic output line; a second N-type thin film transistor having a gate connected to the low potential electrostatic output line and a drain connected to the source of the first N-type thin film transistor, and a source connected to the electrostatic signal input line.

Abstract: A method for intercepting pixel leaked voltages of a display panel is disclosed. The method includes following steps: displaying a black frame at a first display area of the display panel and a white frame at a second display area of the display panel at the same time; intercepting a first pixel light spot, wherein the first pixel light spot is caused by the gate of a transistor leaks a gate voltage to a pixel unit coupled to the transistor while voltage leakage exists between the gate and the source of the transistor within the first display area; intercepting a second pixel light spot, wherein the second pixel light spot is caused by the gate of the transistor leaks a source voltage to the pixel unit coupled to the transistor if the voltage leakage exists between the source and the drain of the transistor within the first display area.

Abstract: A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield can be increased to effectively improve productivity. Heavy and light ion doping can be simultaneously achieved with one single doping operation so that manufacturing cost can be reduced. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to contact the two ends of the active layer thereby effectively reducing contact resistance and improving product yield. Also provided is a TFT substrate manufactured with the method.

Abstract: A GOA driving panel is disclosed. The GOA driving panel includes an active area and a non-active area arranged at two opposite sides of the active area. The non-active area is provided with a plurality of GOA driving units, and each GOA driving unit is connected with one corresponding scanning line in the active area for outputting a scanning signal to the scanning line. The non-active area is further provided with a plurality of signal waveform delay units, and each signal waveform delay unit is arranged between a GOA driving unit and a corresponding scanning line.

Abstract: An electrostatic protection circuit of a display panel includes a first P-type thin film transistor having a gate connected to a high potential electrostatic output line and a drain connected to a high potential electrostatic output line, a second P-type thin film transistor having a gate connected to a high potential electrostatic output line and a drain connected to a source of the first P-type thin film transistor, and a source connected to the electrostatic signal input line; a first N-type thin film transistor having a gate connected to the low potential electrostatic output line, and a drain connected to the low potential electrostatic output line; a second N-type thin film transistor having a gate connected to the low potential electrostatic output line and a drain connected to the source of the first N-type thin film transistor, and a source connected to the electrostatic signal input line.

Abstract: The present disclosure provides an array substrate, the array substrate includes a plurality of array blocks arranged at intervals, wherein each array block includes a plurality of sub-array substrates arranged at intervals, at least one of a periphery of the array substrate, a periphery of the array block, and a periphery of the display area of the sub-array substrate is arranged with an electrostatic protection structure, the electrostatic protection structure is a transparent metal oxide wire, or a metal wire and a transparent conductive metal oxide wire arranged in layers. The existence of the electrostatic protection structure can effectively shield the outside static electricity. The disclosure also provides a liquid crystal display panel adopting the array substrate.

Abstract: A manufacturing method of a TFT substrate uses a bottom gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield and increase productivity are effectively improved. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to get in connection with the two ends of the active layer so as to effectively reduce contact resistance and improve product yield. Also provided is a TFT substrate manufactured with the method.

Abstract: A TFT substrate includes, stacked in sequence from bottom to top, a backing plate, a gate electrode, a gate insulation layer, an active layer and a source electrode and a drain electrode, a first passivation layer, a planarization layer, a common electrode, a second passivation layer, and a pixel electrode. The source electrode and the drain electrode are respectively located at two sides of the active layer. The active layer includes two lightly-ion-doped semiconductor layers respectively connected with the source and drain electrodes and a channel-zone semiconductor layer located therebetween. The first passivation layer and the planarization layer include a first via formed therein and corresponding to the drain electrode. The second passivation layer has a second via extending through a portion of the second passivation layer inside the first via. The pixel electrode is connected through the second via to the drain electrode.

Abstract: A GOA driving panel is disclosed. The GOA driving panel includes a plurality of GOA driving units and a plurality of output capacitors. Each output capacitor is arranged between a GOA driving unit and a corresponding scanning line so that an output waveform of a row scanning signal output by the GOA driving unit is a delay waveform. In the GOA driving unit, a difference among feedback voltages of pixel units in different active areas of the panel can be effectively reduced, whereby image flicker of the panel can be alleviated, and display quality thereof can be improved.

Abstract: The present disclosure provides an array substrate, the array substrate includes a plurality of array blocks arranged at intervals, wherein each array block includes a plurality of sub-array substrates arranged at intervals, at least one of a periphery of the array substrate, a periphery of the array block, and a periphery of the display area of the sub-array substrate is arranged with an electrostatic protection structure, the electrostatic protection structure is a transparent metal oxide wire, or a metal wire and a transparent conductive metal oxide wire arranged in layers. The existence of the electrostatic protection structure can effectively shield the outside static electricity. The disclosure also provides a liquid crystal display panel adopting the array substrate.

Abstract: A GOA driving panel is disclosed. The GOA driving panel includes a plurality of GOA driving units and a plurality of output capacitors. Each output capacitor is arranged between a GOA driving unit and a corresponding scanning line so that an output waveform of a row scanning signal output by the GOA driving unit is a delay waveform. In the GOA driving unit, a difference among feedback voltages of pixel units in different active areas of the panel can be effectively reduced, whereby image flicker of the panel can be alleviated, and display quality thereof can be improved.

Abstract: A manufacturing method of a display panel disclosed by the invention includes: providing a substrate, the substrate having a first metal layer disposed thereon, the substrate including a first display region and a first peripheral region, the first metal layer covering the first display region and the first peripheral region; laying a photoresist layer on the first metal layer to form a first half-finished plate; exposing and developing the first half-finished plate to form a second half-finished plate with first and second preset patterns; etching and stripping the second half-finished plate to form a first preset metal wire group on the first display region and form a second preset metal wire group on the first peripheral region. The invention can significantly reduce the occurrence of electrostatic discharge phenomenon during the manufacturing process of a display panel and thus the yield of the display panel can be greatly improved.

Abstract: A GOA driving panel is disclosed. The GOA driving panel includes an active area and a non-active area arranged at two opposite sides of the active area. The non-active area is provided with a plurality of GOA driving units, and each GOA driving unit is connected with one corresponding scanning line in the active area for outputting a scanning signal to the scanning line. The non-active area is further provided with a plurality of signal waveform delay units, and each signal waveform delay unit is arranged between a GOA driving unit and a corresponding scanning line.

Abstract: A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield can be increased to effectively improve productivity. Heavy and light ion doping can be simultaneously achieved with one single doping operation so that manufacturing cost can be reduced. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to contact the two ends of the active layer thereby effectively reducing contact resistance and improving product yield. Also provided is a TFT substrate manufactured with the method.

Abstract: A manufacturing method of a TFT substrate uses a bottom gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield and increase productivity are effectively improved. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to get in connection with the two ends of the active layer so as to effectively reduce contact resistance and improve product yield. Also provided is a TFT substrate manufactured with the method.