Patents by Inventor Yuanfu Liu

Yuanfu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180224683
    Abstract: A manufacturing method of a TFT substrate uses a bottom gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield and increase productivity are effectively improved. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to get in connection with the two ends of the active layer so as to effectively reduce contact resistance and improve product yield. Also provided is a TFT substrate manufactured with the method.
    Type: Application
    Filed: February 24, 2017
    Publication date: August 9, 2018
    Inventor: Yuanfu Liu
  • Publication number: 20180226438
    Abstract: A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield can be increased to effectively improve productivity. Heavy and light ion doping can be simultaneously achieved with one single doping operation so that manufacturing cost can be reduced. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to contact the two ends of the active layer thereby effectively reducing contact resistance and improving product yield. Also provided is a TFT substrate manufactured with the method.
    Type: Application
    Filed: February 24, 2017
    Publication date: August 9, 2018
    Inventor: Yuanfu Liu
  • Patent number: 9977301
    Abstract: The present invention discloses an array substrate, comprising a first storage capacitor and a second storage capacitor, and the first storage capacitor and the second storage capacitor are coupled in parallel to form a total storage capacitor of the array substrate to increase the total storage capacitor of the array substrate, so as to avoid the issues of the cross talk and the image residue due to the over small total storage capacitor for promoting the quality of the array substrate. The present invention further discloses a display panel utilizing the array substrate and a liquid crystal display panel utilizing the array substrate.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: May 22, 2018
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Yuanfu Liu
  • Publication number: 20180101075
    Abstract: The present invention discloses an array substrate, comprising a first storage capacitor and a second storage capacitor, and the first storage capacitor and the second storage capacitor are coupled in parallel to form a total storage capacitor of the array substrate to increase the total storage capacitor of the array substrate, so as to avoid the issues of the cross talk and the image residue due to the over small total storage capacitor for promoting the quality of the array substrate. The present invention further discloses a display panel utilizing the array substrate and a liquid crystal display panel utilizing the array substrate.
    Type: Application
    Filed: May 4, 2016
    Publication date: April 12, 2018
    Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Yuanfu LIU
  • Patent number: 9716116
    Abstract: Provided is a TFT array substrate, which increases the area of a drain electrode of a TFT within a light-shielding zone to have the drain electrode overlapping a portion of a horizontal projection of a common electrode, wherein the drain electrode and the common electrode constitute a first storage capacitor and a pixel electrode and the common electrode constitute a second storage capacitor. The pixel electrode and the drain electrode are electrically connected and thus are of the same potential. The first storage capacitor and the second storage capacitor are connected in parallel and collectively form a storage capacitor such that the storage capacitor has a capacity that is equal to the sum of capacities of the first storage capacitor and the second storage capacitor, whereby, without reducing aperture ratio, the capacity of the storage capacitor is increased, crosstalk and image sticking are alleviated, and product display quality is enhanced.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 25, 2017
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuanfu Liu
  • Publication number: 20170207251
    Abstract: Provided is a TFT array substrate, which increases the area of a drain electrode of a TFT within a light-shielding zone to have the drain electrode overlapping a portion of a horizontal projection of a common electrode, wherein the drain electrode and the common electrode constitute a first storage capacitor and a pixel electrode and the common electrode constitute a second storage capacitor. The pixel electrode and the drain electrode are electrically connected and thus are of the same potential. The first storage capacitor and the second storage capacitor are connected in parallel and collectively form a storage capacitor such that the storage capacitor has a capacity that is equal to the sum of capacities of the first storage capacitor and the second storage capacitor, whereby, without reducing aperture ratio, the capacity of the storage capacitor is increased, crosstalk and image sticking are alleviated, and product display quality is enhanced.
    Type: Application
    Filed: April 25, 2016
    Publication date: July 20, 2017
    Inventor: Yuanfu Liu
  • Publication number: 20170200750
    Abstract: Provided is a method for manufacturing an array substrate, in which a planarization layer mask includes a strip pattern that is provided for forming a groove and has two opposite sides along which taper modification patterns are provided so as to reduce taper of a groove formed in a planarization layer, making a slope thereof less steep, thereby preventing shorting of signal lines caused by residues of metal or ITO in a subsequent operation and thus increasing product yield. For the groove associated portion of an array substrate involving an in-cell touch structure, there is no need to change line for the touch sensing lines so as to lower down the difficulty of the operation and increase product yield.
    Type: Application
    Filed: April 25, 2016
    Publication date: July 13, 2017
    Inventors: Yuanfu Liu, Fuhsiung Tang
  • Publication number: 20170154904
    Abstract: A manufacturing method of a display panel disclosed by the invention includes: providing a substrate, the substrate having a first metal layer disposed thereon, the substrate including a first display region and a first peripheral region, the first metal layer covering the first display region and the first peripheral region; laying a photoresist layer on the first metal layer to form a first half-finished plate; exposing and developing the first half-finished plate to form a second half-finished plate with first and second preset patterns; etching and stripping the second half-finished plate to form a first preset metal wire group on the first display region and form a second preset metal wire group on the first peripheral region. The invention can significantly reduce the occurrence of electrostatic discharge phenomenon during the manufacturing process of a display panel and thus the yield of the display panel can be greatly improved.
    Type: Application
    Filed: August 14, 2015
    Publication date: June 1, 2017
    Applicant: Shenzhen China Star OptoelectronicsTechnology Co. Ltd.
    Inventor: Yuanfu LIU
  • Patent number: 9508745
    Abstract: An array substrate and a fabricating method thereof are disclosed. The array substrate has a transparent substrate, a buffer layer, a first/second gate pattern, a transparent insulating layer and a first/second polysilicon pattern. The buffer layer is located on first/second portions of the transparent substrate. The first/second gate patterns are formed on the buffer layer and located respectively on the first/second portions. The transparent insulating layer covers the first/second gate patterns and the buffer layer. The first/second polysilicon patterns are formed on the transparent insulating layer, and have neighboring first/second regions and neighboring third/fourth regions; the second/fourth regions are first/second lightly doped polysilicon regions respectively; the first region and the first gate pattern have an identical first patterning shape; and the third region and the second gate pattern have an identical second patterning shape.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: November 29, 2016
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO. LTD.
    Inventor: Yuanfu Liu