Patents by Inventor Yuangang Wang

Yuangang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210212362
    Abstract: An ultrasonic electronic cigarette is disclosed. The electronic cigarette includes an atomizer (1) and a battery assembly (2) detachably connected to each other. The atomizer (1) comprises an ultrasonic atomization sheet (3), and the battery assembly (2) comprises a first battery electrode (4) and a second battery electrode (5) for supplying power to the atomizer (1). When the atomizer (1) is connected to the battery assembly (2), a first pole of the ultrasonic atomization sheet (3) is electrically connected to the first battery electrode (4), and a second pole of the ultrasonic atomization sheet (3) is electrically connected to the second battery electrode (5).
    Type: Application
    Filed: December 7, 2018
    Publication date: July 15, 2021
    Applicant: CHINA TOBACCO HUNAN INDUSTRIAL CO., LTD.
    Inventors: Jianfu Liu, Kejun Zhong, Xiaoyi Guo, Wei Huang, Hong Yu, Yuangang Dai, Xinqiang Yin, Jianhua Yi, Yongquan Zhou, Yang Wang
  • Patent number: 11029848
    Abstract: A file management method, a distributed storage system, and a management node are disclosed. In the distributed storage system, after receiving a file creation request sent by a host for requesting to create a file in a distributed storage system, a management node allocates, to the file, first virtual space from global virtual address space of the distributed storage system, where local virtual address space of each storage node in the distributed storage system is corresponding to a part of the global virtual address space. Then, the management node records metadata of the file, where the metadata of the file includes information about the first virtual space, and the information about the first virtual space is used to point to local virtual address space of a storage node that is used to store the file. Further, the management node sends, the information about the first virtual space to the host.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 8, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jun Xu, Junfeng Zhao, Yuangang Wang
  • Publication number: 20210098628
    Abstract: The disclosure provides a normally-off gallium oxide field-effect transistor structure and a preparation method therefor, and relates to the technical field of semiconductor device. The normally-off gallium oxide field-effect transistor structure comprises a substrate layer and an n-type doped gallium oxide channel layer from bottom to top. The n-type doped gallium oxide channel layer is provided with a source, a drain, and a gate. The gate is located between the source and the drain. A no-electron channel region is provided in the n-type doped gallium oxide channel layer located below the gate.
    Type: Application
    Filed: October 1, 2020
    Publication date: April 1, 2021
    Inventors: Yuanjie Lv, Yuangang Wang, Xingye Zhou, Xin Tan, Xubo Song, Shixiong Liang, Zhihong Feng
  • Patent number: 10956077
    Abstract: A data access method, a routing apparatus, and a storage system are provided. The method is applied to a storage system including a first storage device, a second storage device, and a routing apparatus. A logical unit in each storage device includes at least one first-type logical block and at least one second-type logical block. According to the method, when sending access requests to the storage devices in the storage system according to a preset rule, the routing apparatus sends access requests corresponding to same target logical blocks to one of the storage devices according to a preset rule. This reduces network overheads between the storage system and the application server, and improves efficiency of processing the access requests by the storage system.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: March 23, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Tianxiang Li, Jun Xu, Yuangang Wang
  • Publication number: 20210043778
    Abstract: The disclosure is applicable for the technical field of semiconductor devices manufacturing, and provides a gallium oxide SBD terminal structure. The gallium oxide SBD terminal structure comprises a cathode metal layer, an N+ high-concentration substrate layer, an N? low-concentration Ga2O3 epitaxial layer and an anode metal layer from bottom to top, wherein the N? low-concentration Ga2O3 epitaxial layer is within a range of certain thickness close to the anode metal layer; and a doping concentration below the anode metal layer is greater than a doping concentration on two sides of the anode metal layer. Namely, only a doping concentration of the part outside the corresponding area of the anode metal layer is changed, so that the breakdown voltage of the gallium oxide SBD terminal structure is improved under the condition of guaranteeing low on resistance.
    Type: Application
    Filed: October 13, 2020
    Publication date: February 11, 2021
    Inventors: Yuanjie LV, Yuangang Wang, Xingye Zhou, Xin Tan, Xubo Song, Xuefeng Zou, Shixiong Liang, Zhihong Feng
  • Publication number: 20210036177
    Abstract: A method for preparing an avalanche photodiode includes preparing a mesa on a wafer, growing a sacrificial layer on an upper surface of the wafer and a side surface of the mesa, removing the sacrificial layer in an ohmic contact electrode region of the wafer, preparing an ohmic contact electrode in the ohmic contact electrode region of the wafer, removing the sacrificial layer in a non-mesa region of the wafer, growing a passivation layer on the upper surface of the wafer and the side surface of the mesa, removing the passivation layer on the upper surface of the mesa of the wafer and the passivation layer in the non-mesa region of the wafer corresponding to the ohmic contact electrode region, and removing the sacrificial layer on the upper surface of the mesa of the wafer.
    Type: Application
    Filed: September 24, 2020
    Publication date: February 4, 2021
    Inventors: Xingye Zhou, Zhihong Feng, Yuanjie LV, Xin Tan, Yuangang Wang, Xubo Song, Jia Li, Yulong Fang
  • Patent number: 10908833
    Abstract: A data migration method for a storage system after expansion and a storage system are provided. After an ith expansion is performed on the storage system, data migration is performed by using an auxiliary balanced incomplete block design. Because a quantity of tuples including any element in the auxiliary balanced incomplete block design is identical, and each migration unit includes an identical quantity of parity chunks, a data migration amount after the expansion is minimized. In this way, time required for data migration after the expansion is significantly reduced, and a delay in a response to a user request that is caused because a data migration operation needs to be performed after the expansion is also reduced.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: February 2, 2021
    Assignees: Huawei Technologies Co., Ltd., University of Science and Technology of China
    Inventors: Yinlong Xu, Zhipeng Li, Yuangang Wang
  • Publication number: 20210020801
    Abstract: The disclosure is related to the technical field of semiconductors, and provides a method for manufacturing a tilted mesa and a method for manufacturing a detector. The method for manufacturing a tilted mesa comprises: coating a photoresist layer on a mesa region of a chip; heating the chip on which the photoresist layer is coated from a first preset temperature to a second preset temperature; performing etching processing on the heated chip, so as to manufacture a mesa having a preset tilting angle; and removing the photoresist layer on the mesa region of the chip after the mesa is manufactured.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 21, 2021
    Inventors: Xingye Zhou, Zhihong Feng, Yuanjie LV, Xin Tan, Xubo Song, Jia Li, Yulong Fang, Yuangang Wang
  • Publication number: 20210020802
    Abstract: The disclosure provides a silicon carbide detector and a preparation method therefor. The silicon carbide detector comprises: a wafer, the wafer sequentially comprises, from bottom to top, a substrate, a silicon carbide P+ layer, an N-type silicon carbide insertion layer, an N+ type silicon carbide multiplication layer, an N-type silicon carbide absorption layer and a silicon carbide N+ layer; the doping concentration of the N-type silicon carbide insertion layer gradually increases from bottom to top, and the doping concentration of the N-type silicon carbide absorption layer gradually decreases from bottom to top; a mesa is etched on the wafer, and the mesa is etched to an upper surface of the silicon carbide P+ layer; an N-type electrode is arranged on an upper surface of the mesa, and a P-type electrode is arranged on an upper surface of a non-mesa region.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 21, 2021
    Inventors: Xingye Zhou, Zhihong Feng, Yuanjie LV, Xin Tan, Yuangang Wang, Xubo Song, Jia Li, Yulong Fang
  • Publication number: 20210013027
    Abstract: The present disclosure discloses a method for preparing an isolation area of a gallium oxide device, the method comprising: depositing a mask layer on a gallium oxide material; removing a preset portion region of the mask layer; preparing an isolation area in a position, corresponding to the preset portion region, on the gallium oxide material by using a high-temperature oxidation technique, with the isolation area being located between active areas of the gallium oxide device; and removing the remaining mask layer on the gallium oxide material. In the disclosure, the isolation area is prepared by using the high-temperature oxidation technique, which prevents damage to the gallium oxide device during the preparation of the isolation area, thereby achieving isolation between the active areas of the gallium oxide device.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Yuanjie LV, Yuangang Wang, Xingye Zhou, Xin Tan, Xubo Song, Shixiong Liang, Zhihong Feng
  • Patent number: 10854741
    Abstract: An enhanced HFET, comprising a HFET device body.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 1, 2020
    Assignee: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS
    Inventors: Yuangang Wang, Zhihong Feng, Yuanjie Lv, Xin Tan, Xubo Song, Xingye Zhou, Yulong Fang, Guodong Gu, Hongyu Guo, Shujun Cai
  • Publication number: 20200373390
    Abstract: The disclosure provides a method for preparing a self-aligned surface channel field effect transistor, and provides a power device. The method includes the following steps: depositing a first metal mask layer; preparing a first photoresist layer; forming a source area pattern and a drain area pattern; depositing a source metal layer and a drain metal layer on the source area pattern and the drain area pattern; peeling off and removing the first photoresist layer; depositing a second metal mask layer; preparing a second photoresist layer, and forming at least one gate area pattern closer toward the source metal layer by performing exposure and development; removing the first metal mask layer and the second metal mask layer between the source metal layer and the drain metal layer by a wet corrosion; depositing a gate metal layer on the gate area pattern; and peeling off and removing the second photoresist layer.
    Type: Application
    Filed: March 28, 2019
    Publication date: November 26, 2020
    Inventors: Yuangang WANG, Yuanjie LV, Zhihong FENG, Cui YU, Chuangjie ZHOU, Zezhao HE, Xubo SONG, Shixiong LIANG
  • Publication number: 20200356270
    Abstract: A storage system includes a management node and a plurality of storage nodes forming a redundant array of independent disks (RAID). When the management node determines that not all data in an entire stripe is updated based on a received write request, the management node sends update data chunk obtained from to-be-written data to corresponding storage node. The storage node do not directly update, based on the received update data chunks, data block stored in storage device of the storage node, but store the update data chunk into non-volatile memories (NVM) cache of the storage node and send the update data chunk to another storage node to backup. According to the data updating method, write amplification problems caused in a stripe update process can be reduced, thereby improving update performance of the storage system.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Qun Yu, Jun Xu, Yuangang Wang
  • Patent number: 10831677
    Abstract: A cache management method, a cache controller, and a computer system are provided. In the method, the cache controller obtains an operation instruction; when a destination address in the operation instruction hits no cache line cache line in a cache of the computer system, and the cache includes no idle cache line, the cache controller selects a to-be-replaced cache line from a replacement set, where the replacement set includes at least two cache lines; and the cache controller eliminates the to-be-replaced cache line from the cache, and stores, in the cache, a cache line obtained from the destination address. According to the cache management method, system overheads of cache line replacement can be reduced, and cache line replacement efficiency can be improved.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: November 10, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jun Xu, Yongbing Huang, Yuangang Wang
  • Patent number: 10796774
    Abstract: A flash memory controller refreshes memory blocks in a flash memory device by setting different refresh cycles for individual memory blocks in the flash memory device. The flash memory controller records a number of erase operations performed on each memory block of the flash memory device. Upon detecting that a bit error rate of a memory block is greater than a preset threshold, the flash memory controller determines a refresh cycle for the memory block based on recorded number of erase operations performed on the memory block, and then refreshes the memory block according to the refresh cycle.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 6, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Liang Shi, Yejia Di, Hsing Mean Sha, Yuangang Wang, Dongfang Shan
  • Publication number: 20200312992
    Abstract: The present disclosure relates to semiconductor devices, and in particular, to an enhancement-mode field effect transistor. This enhancement-mode field effect transistor includes a substrate, a channel layer formed on an upper surface of the substrate, a source electrode and a drain electrode respectively formed on both sides of the channel layer, and a gate electrode formed on an upper surface of the channel layer, a region outside the corresponding region of the gate electrode in the channel layer is provided with a carrier-free region. Carriers are absent in the carrier-free region, and carriers are present in the remaining portion of the channel layer.
    Type: Application
    Filed: December 27, 2017
    Publication date: October 1, 2020
    Inventors: Yuanjie LV, Yuangang Wang, Xubo Song, Xin Tan, Xingye Zhou, Zhihong Feng
  • Publication number: 20200250091
    Abstract: An access request processing method is performed by a computer device that includes a processor, a dynamic random-access memory (DRAM), and a non-volatile memory (NVM). When receiving a write request, the processor may identify an object cache page according to the write request. The processor obtains the to-be-written data from a buffer according to a buffer pointer in the write request, the to-be-written data including a new data chunk to be written into the object cache page. The processor then inserts a new data node into a log chain of the object cache page, where the NVM stores data representing the log chain of the object cache page. The new data node includes information regarding the new data chunk of the object cache page. The computer device provided in this application can reduce system overheads while protecting data consistency.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jun Xu, Qun Yu, Yuangang Wang
  • Patent number: 10733101
    Abstract: A processing node, a computer system, and a transaction conflict detection method, where the processing node includes a processor and a transactional cache. When obtaining a first operation instruction in a transaction for accessing shared data, the processor accesses the transactional cache for caching shared data of a transaction processed by the processing node. If the transactional cache determines that the first operation instruction fails to hit a cache line in the transactional cache, the transactional cache sends a first destination address in the operation instruction to a transactional cache in another processing node. After receiving status information of a cache line hit by the first destination address from the other processing node, the transactional cache determines, based on the received status information, whether the first operation instruction conflicts with a second operation instruction executed by the other processing node.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 4, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hao Xiao, Yuangang Wang, Jun Xu
  • Patent number: 10732898
    Abstract: A method for accessing a flash memory device and a flash memory device. After receiving a write request for an address, a flash memory controller obtains an indicator of the address, where the indicator indicates a last access type of the address, which might be a write operation or a read operation. When determining the indicator indicates a write operation, which means the access type for the address is normally write operation, to save time, the flash memory controller perform a fast-write operation on the address, when the indicator indicates a read operation, which means there might be plenty of read operations on the address, to facilitate future read operation, the controller performs a slow-write operation on the address.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: August 4, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Liang Shi, Chun Xue, Qiao Li, Dongfang Shan, Jun Xu, Yuangang Wang
  • Patent number: 10725662
    Abstract: A storage system includes a management node and a plurality of storage nodes forming a redundant array of independent disks (RAID). When the management node determines that not all data in an entire stripe is updated based on a received write request, the management node sends update data chunk obtained from to-be-written data to corresponding storage node. The storage node do not directly update, based on the received update data chunks, data block stored in storage device of the storage node, but store the update data chunk into non-volatile memories (NVM) cache of the storage node and send the update data chunk to another storage node to backup. According to the data updating method, write amplification problems caused in a stripe update process can be reduced, thereby improving update performance of the storage system.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: July 28, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Qun Yu, Jun Xu, Yuangang Wang