Patents by Inventor Yuanjie Lv

Yuanjie Lv has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098628
    Abstract: The disclosure provides a normally-off gallium oxide field-effect transistor structure and a preparation method therefor, and relates to the technical field of semiconductor device. The normally-off gallium oxide field-effect transistor structure comprises a substrate layer and an n-type doped gallium oxide channel layer from bottom to top. The n-type doped gallium oxide channel layer is provided with a source, a drain, and a gate. The gate is located between the source and the drain. A no-electron channel region is provided in the n-type doped gallium oxide channel layer located below the gate.
    Type: Application
    Filed: October 1, 2020
    Publication date: April 1, 2021
    Inventors: Yuanjie Lv, Yuangang Wang, Xingye Zhou, Xin Tan, Xubo Song, Shixiong Liang, Zhihong Feng
  • Publication number: 20210043778
    Abstract: The disclosure is applicable for the technical field of semiconductor devices manufacturing, and provides a gallium oxide SBD terminal structure. The gallium oxide SBD terminal structure comprises a cathode metal layer, an N+ high-concentration substrate layer, an N? low-concentration Ga2O3 epitaxial layer and an anode metal layer from bottom to top, wherein the N? low-concentration Ga2O3 epitaxial layer is within a range of certain thickness close to the anode metal layer; and a doping concentration below the anode metal layer is greater than a doping concentration on two sides of the anode metal layer. Namely, only a doping concentration of the part outside the corresponding area of the anode metal layer is changed, so that the breakdown voltage of the gallium oxide SBD terminal structure is improved under the condition of guaranteeing low on resistance.
    Type: Application
    Filed: October 13, 2020
    Publication date: February 11, 2021
    Inventors: Yuanjie LV, Yuangang Wang, Xingye Zhou, Xin Tan, Xubo Song, Xuefeng Zou, Shixiong Liang, Zhihong Feng
  • Publication number: 20210036177
    Abstract: A method for preparing an avalanche photodiode includes preparing a mesa on a wafer, growing a sacrificial layer on an upper surface of the wafer and a side surface of the mesa, removing the sacrificial layer in an ohmic contact electrode region of the wafer, preparing an ohmic contact electrode in the ohmic contact electrode region of the wafer, removing the sacrificial layer in a non-mesa region of the wafer, growing a passivation layer on the upper surface of the wafer and the side surface of the mesa, removing the passivation layer on the upper surface of the mesa of the wafer and the passivation layer in the non-mesa region of the wafer corresponding to the ohmic contact electrode region, and removing the sacrificial layer on the upper surface of the mesa of the wafer.
    Type: Application
    Filed: September 24, 2020
    Publication date: February 4, 2021
    Inventors: Xingye Zhou, Zhihong Feng, Yuanjie LV, Xin Tan, Yuangang Wang, Xubo Song, Jia Li, Yulong Fang
  • Publication number: 20210020801
    Abstract: The disclosure is related to the technical field of semiconductors, and provides a method for manufacturing a tilted mesa and a method for manufacturing a detector. The method for manufacturing a tilted mesa comprises: coating a photoresist layer on a mesa region of a chip; heating the chip on which the photoresist layer is coated from a first preset temperature to a second preset temperature; performing etching processing on the heated chip, so as to manufacture a mesa having a preset tilting angle; and removing the photoresist layer on the mesa region of the chip after the mesa is manufactured.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 21, 2021
    Inventors: Xingye Zhou, Zhihong Feng, Yuanjie LV, Xin Tan, Xubo Song, Jia Li, Yulong Fang, Yuangang Wang
  • Publication number: 20210020802
    Abstract: The disclosure provides a silicon carbide detector and a preparation method therefor. The silicon carbide detector comprises: a wafer, the wafer sequentially comprises, from bottom to top, a substrate, a silicon carbide P+ layer, an N-type silicon carbide insertion layer, an N+ type silicon carbide multiplication layer, an N-type silicon carbide absorption layer and a silicon carbide N+ layer; the doping concentration of the N-type silicon carbide insertion layer gradually increases from bottom to top, and the doping concentration of the N-type silicon carbide absorption layer gradually decreases from bottom to top; a mesa is etched on the wafer, and the mesa is etched to an upper surface of the silicon carbide P+ layer; an N-type electrode is arranged on an upper surface of the mesa, and a P-type electrode is arranged on an upper surface of a non-mesa region.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 21, 2021
    Inventors: Xingye Zhou, Zhihong Feng, Yuanjie LV, Xin Tan, Yuangang Wang, Xubo Song, Jia Li, Yulong Fang
  • Publication number: 20210013027
    Abstract: The present disclosure discloses a method for preparing an isolation area of a gallium oxide device, the method comprising: depositing a mask layer on a gallium oxide material; removing a preset portion region of the mask layer; preparing an isolation area in a position, corresponding to the preset portion region, on the gallium oxide material by using a high-temperature oxidation technique, with the isolation area being located between active areas of the gallium oxide device; and removing the remaining mask layer on the gallium oxide material. In the disclosure, the isolation area is prepared by using the high-temperature oxidation technique, which prevents damage to the gallium oxide device during the preparation of the isolation area, thereby achieving isolation between the active areas of the gallium oxide device.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Yuanjie LV, Yuangang Wang, Xingye Zhou, Xin Tan, Xubo Song, Shixiong Liang, Zhihong Feng
  • Patent number: 10854741
    Abstract: An enhanced HFET, comprising a HFET device body.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 1, 2020
    Assignee: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS
    Inventors: Yuangang Wang, Zhihong Feng, Yuanjie Lv, Xin Tan, Xubo Song, Xingye Zhou, Yulong Fang, Guodong Gu, Hongyu Guo, Shujun Cai
  • Publication number: 20200373390
    Abstract: The disclosure provides a method for preparing a self-aligned surface channel field effect transistor, and provides a power device. The method includes the following steps: depositing a first metal mask layer; preparing a first photoresist layer; forming a source area pattern and a drain area pattern; depositing a source metal layer and a drain metal layer on the source area pattern and the drain area pattern; peeling off and removing the first photoresist layer; depositing a second metal mask layer; preparing a second photoresist layer, and forming at least one gate area pattern closer toward the source metal layer by performing exposure and development; removing the first metal mask layer and the second metal mask layer between the source metal layer and the drain metal layer by a wet corrosion; depositing a gate metal layer on the gate area pattern; and peeling off and removing the second photoresist layer.
    Type: Application
    Filed: March 28, 2019
    Publication date: November 26, 2020
    Inventors: Yuangang WANG, Yuanjie LV, Zhihong FENG, Cui YU, Chuangjie ZHOU, Zezhao HE, Xubo SONG, Shixiong LIANG
  • Publication number: 20200312992
    Abstract: The present disclosure relates to semiconductor devices, and in particular, to an enhancement-mode field effect transistor. This enhancement-mode field effect transistor includes a substrate, a channel layer formed on an upper surface of the substrate, a source electrode and a drain electrode respectively formed on both sides of the channel layer, and a gate electrode formed on an upper surface of the channel layer, a region outside the corresponding region of the gate electrode in the channel layer is provided with a carrier-free region. Carriers are absent in the carrier-free region, and carriers are present in the remaining portion of the channel layer.
    Type: Application
    Filed: December 27, 2017
    Publication date: October 1, 2020
    Inventors: Yuanjie LV, Yuangang Wang, Xubo Song, Xin Tan, Xingye Zhou, Zhihong Feng
  • Patent number: 10505024
    Abstract: A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: December 10, 2019
    Assignee: The 13th Research Institute of China Electronics Technology Group Corporation
    Inventors: Yuanjie Lv, Xubo Song, Zhihong Feng, Yuangang Wang, Xin Tan, xingye Zhou
  • Publication number: 20190027590
    Abstract: A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.
    Type: Application
    Filed: October 27, 2017
    Publication date: January 24, 2019
    Inventors: Yuanjie Lv, Xubo Song, Zhihong Feng, Yuangang Wang, Xin Tan, xingye Zhou