Patents by Inventor Yuanjie Lv

Yuanjie Lv has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for preparing cap-layer-structured gallium oxide field effect transistor
    Patent number: 10505024
    Abstract: A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: December 10, 2019
    Assignee: The 13th Research Institute of China Electronics Technology Group Corporation
    Inventors: Yuanjie Lv, Xubo Song, Zhihong Feng, Yuangang Wang, Xin Tan, xingye Zhou
  • METHOD FOR PREPARING CAP-LAYER-STRUCTURED GALLIUM OXIDE FIELD EFFECT TRANSISTOR
    Publication number: 20190027590
    Abstract: A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.
    Type: Application
    Filed: October 27, 2017
    Publication date: January 24, 2019
    Inventors: Yuanjie Lv, Xubo Song, Zhihong Feng, Yuangang Wang, Xin Tan, xingye Zhou