Patents by Inventor Yuanning Yu

Yuanning Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240369759
    Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 12132024
    Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, an insulating encapsulation, and a plurality of conductive pillars. The second semiconductor die is located on and electrically communicates to the first semiconductor die through joints therebetween. The insulating encapsulation encapsulates the first semiconductor die and the second semiconductor die and covers the joints. The plurality of conductive pillars is next to and electrically connected to the first semiconductor die and the second semiconductor die, and is covered by the insulating encapsulation.
    Type: Grant
    Filed: August 29, 2021
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Tzuan-Horng Liu, Cheng-Chieh Hsieh, Tsung-Yuan Yu
  • Publication number: 20240350985
    Abstract: A system includes a storage tank, a first gas injection unit, a second gas injection unit, a concentration sensor, a dynamic control unit, and a data processing and analysis module. The storage tank is configured to hold a chemical liquid used in etching processes. The first gas injection unit includes a first gas pipe configured to inject a first gas into the storage tank, and a first adjustable valve mounted on the first gas pipe. The second gas injection unit includes a second gas pipe configured to inject a second gas into the storage tank, and a second adjustable valve mounted on the second gas pipe. The concentration sensor is connected to the storage tank. The dynamic control unit electrically connected to the first and second adjustable valves and the concentration sensor. The data processing and analysis module integrated with the dynamic control unit.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 24, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu KUO, Shang-Yun HUANG, Weibo YU, Shang-Yuan YU
  • Publication number: 20240355388
    Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, Maybe Chen, Ya-Chin King, Wen Zhang Lin, Chrong Jung Lin, Hsin-Yuan Yu
  • Patent number: 12117449
    Abstract: The present disclosure provides the use of BAZ1B_K426hy in the preparation of a product for tumor detection and belongs to the field of biotechnology. The present disclosure further provides a group of immunogenic polypeptides, including polypeptide A and polypeptide B. An anti-BAZ1B_K426hy polyclonal antibody is prepared by conducting mixed immunization on an animal with the immunogenic polypeptide. The polyclonal antibody can specifically recognize an endogenous protein BAZ1B_K426hy by enzyme-linked immunosorbent assay (ELISA)/Dot blot/Western blot, which is used for preparation of detection products for tumors and Williams syndrome.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: October 15, 2024
    Assignees: Tangshan People's Hospital, North China University of Science and Technology, Tangshan Maternal And Child Health Hospital
    Inventors: Jingwu Li, Yufeng Li, Shuqing Wang, Jinghua Zhang, Jinghua Wu, Fen Hu, Yuan Yu, Yan Liu, Yuhui Li, Xuan Zheng
  • Publication number: 20240338491
    Abstract: The present invention is directed to an automated methodology based on GNN to model IC and mitigate hardware security threats. The present invention features a system for detecting hardware Trojans and IP piracy in a circuit. The system may be based on a GNN. The system may convert a plurality of base-level files from the circuit into a graph, convert this graph into a vectorized graph embedding through the use of the GNN, and use the vectorized graph embedding to identify and remedy potential hardware Trojans as well as identify potential IP piracy between two different circuits.
    Type: Application
    Filed: August 16, 2022
    Publication date: October 10, 2024
    Inventors: Mohammad Abdullah Al Faruque, Rozhin Yasaei, Shih-Yuan Yu
  • Publication number: 20240332282
    Abstract: A device includes a first circuit region including a nanostructure device and a second circuit region offset from the first circuit region. The nanostructure device has a vertical stack of nanostructures disposed in a plurality of first semiconductor layers and a gate structure wrapping around the nanostructures of the vertical stack. The second circuit region includes a bipolar junction device electrically connected to the nanostructure device and at least one diode electrically connected between a collector and a base of the bipolar junction device. At least one implant region extends through the plurality of first semiconductor layers and a plurality of second semiconductor layers that are disposed between respective vertically neighboring pairs of the plurality of first semiconductor layers. A backside interconnect structure is electrically connected to a source/drain region of the nanostructure device.
    Type: Application
    Filed: April 3, 2023
    Publication date: October 3, 2024
    Inventors: Hsin-Yuan YU, Ming-Shuan LI, Wun-Jie LIN
  • Patent number: 12105323
    Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: October 1, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 12107673
    Abstract: Certain aspects of the present disclosure generally relate to jamming detection for radio frequency (RF) front-end circuitry. For example, certain aspects provide an apparatus having a first counter configured to count a number of times that a power of a reception signal exceeds a first threshold. The apparatus also includes a second counter configured to count a number of measurements of the power of the reception signal. The apparatus further includes control logic having a first input coupled to an output of the first counter and having a second input coupled to an output of the second counter. The control logic is configured to determine an amount of jamming over a measurement window based on the number of times that the power of the reception signal exceeds the first threshold and on the number of measurements.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: October 1, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Peter Shah, Ajay Devadatta Kanetkar, Siavash Ekbatani, Yuanning Yu, Shrenik Patel, Dongjiang Qiao, Rajagopalan Rangarajan
  • Patent number: 12088372
    Abstract: A method for wireless communication at a wireless device is disclosed herein. The method includes selecting a wideband precoder for a first set of antennas and a second set of antennas based on at least one matrix, where a number of the first set of antennas and the second set of antennas is greater than a maximum number of supported layers. The method includes calculating, based on the selected wideband precoder, a first set of performance metrics for the first set of antennas and a second set of performance metrics for the second set of antennas. The method includes combining the first set of performance metrics for the first set of antennas and the second set of performance metrics for the second set of antennas based on the calculation.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: September 10, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chitaranjan Pelur Sukumar, Ahmed Omar Desouky Ali, Yuanning Yu, Qiang Shen
  • Publication number: 20240282721
    Abstract: A package structure includes a first package. The first package has an active region and a peripheral region surrounding the active region. The first package includes a first redistribution structure, a second redistribution structure, a die, an encapsulant, and a seal ring structure. The second redistribution structure is disposed over the first redistribution structure. The die is disposed in the active region and is located between the first redistribution structure and the second redistribution structure. The encapsulant laterally encapsulates the die. The seal ring structure is disposed in the peripheral region. A first portion of the seal ring structure is embedded in the first redistribution structure, and a second portion of the seal ring structure is embedded in the second redistribution structure.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Tzuan-Horng Liu, Yen-Liang Lin
  • Publication number: 20240283520
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may select a maximum supported rank for reception that is capped based at least in part on one or more impacted antennas of the UE that are unavailable due to sounding reference signal (SRS) switching that switched at least one antenna of the UE. The UE may transmit an indication of the maximum supported rank. The UE may receive a selected rank that is no greater than the maximum supported rank. The UE may receive, from one or more non-impacted antennas of the UE, a communication using the selected rank. Numerous other aspects are described, such as downlink blanking, desensing parameters, canceling SRS switching, and uplink blanking for impacted antennas.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Inventors: Yusuf Said EROGLU, Enoch Shiao-Kuang LU, Pranay Sudeep RUNGTA, Prasanna MADHUSUDHANAN, Yuanning YU, Tae Min KIM, Paolo MINERO
  • Publication number: 20240282686
    Abstract: A method includes forming a first package component and a second package component. The first package component includes a first polymer layer, and a first electrical connector, with at least a part of the first electrical connector being in the first polymer layer. The second package component comprises a second polymer layer, and a second electrical connector, with at least a part of the second electrical connector being in the second polymer layer. The first package component is bonded to the second package component, with the first polymer layer being bonded to the second polymer layer, and the first electrical connector being bonded to the second electrical connector.
    Type: Application
    Filed: June 1, 2023
    Publication date: August 22, 2024
    Inventors: Tzuan-Horng Liu, An-Jhih Su, Hao-Yi Tsai, Tsung-Yuan Yu, Po-Yuan Teng, Chung-Ming Weng, Che-Hsiang Hsu
  • Publication number: 20240274590
    Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.
    Type: Application
    Filed: April 29, 2024
    Publication date: August 15, 2024
    Inventors: Chen-Hua Yu, Hung-Yi Kuo, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Yuan Yu, Ming Hung Tseng
  • Patent number: 12053745
    Abstract: Chemical liquid is injected into a tank. A concentration of a first gas dissolved in the chemical liquid is detected. Based on the detected concentration of the first gas, at least one of the first gas and a second gas is injected into the tank to sustain at least one of the concentration of the first gas and a concentration of the second gas in a range of a target value.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Kuo, Shang-Yun Huang, Weibo Yu, Shang-Yuan Yu
  • Patent number: 12055500
    Abstract: A method and corresponding apparatus are provided for measuring neutron spin precession in an electric field with high sensitivity suitable for practical applications in non-destructive testing, imaging, and the like. Production of a neutron beam with a polarization vector P is followed by transmitting the spin-polarized neutron beam through a sample region in which there is a target generating an electric field, polarization-analyzing the transmitted neutron beam with an analyzing direction orthogonal to P, detecting an intensity of the polarization-analyzed neutron beam; and mapping the detected neutron-beam intensity to a field-strength value for the target electric field.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: August 6, 2024
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventor: Yuan-Yu Jau
  • Patent number: 12051466
    Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, Maybe Chen, Ya-chin King, Wen Zhang Lin, Chrong Jung Lin, Hsin-Yuan Yu
  • Patent number: 12044844
    Abstract: An calibration kit includes a base, a combination of calibration parts, and a manipulation part. The combination of calibration parts is disposed on the base and includes a first calibration part and a second calibration part. The first calibration part has a first calibration surface. The second calibration part has a second calibration surface. The first calibration part and the second calibration part are relatively movable in a movement direction and are movable relative to the base. The manipulation part is movably or rotatably disposed on the base. The manipulation part is configured to be operable to drive the first calibration part and the second calibration part to move in the movement direction relative to the base, so that the combination of calibration parts forms a three-dimensional calibration surface configuration through the first calibration surface and the second calibration surface.
    Type: Grant
    Filed: September 6, 2021
    Date of Patent: July 23, 2024
    Assignee: Qisda Corporation
    Inventors: Tzu-Huan Hsu, Po-Fu Wu, Yuan-Yu Hsiao, Ching-Huey Wang, Chih-Kang Peng, Chun-Ming Shen, Chih-Ming Hu, Yi-Ling Lo
  • Patent number: 12036551
    Abstract: The present disclosure provides a microfluidic device, including a bottom substrate, an electrowetting-on-dielectric (EWOD) chip, a circuit board, a dielectric film, and a motor. The EWOD chip is disposed on the bottom substrate, and the circuit board is arranged on the EWOD chip. The circuit board includes a circuit area that is electrically connected to the EWOD chip, and the empty area is adjacent to the circuit area and the EWOD chip is exposed. The dielectric film is disposed on the empty area of the circuit board and covers the exposed EWOD chip. The motor is disposed under the bottom substrate, and one end of the motor has a magnetic structure, so that the magnetic structure can move closer to or away from the bottom substrate.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: July 16, 2024
    Assignee: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: Shau-Chun Wang, Lai-Kwan Chau, Yuan-Yu Chen
  • Publication number: 20240230653
    Abstract: The present disclosure provides the use of BAZ1B_K426hy in the preparation of a product for tumor detection and belongs to the field of biotechnology. The present disclosure further provides a group of immunogenic polypeptides, including polypeptide A and polypeptide B. An anti-BAZ1B_K426hy polyclonal antibody is prepared by conducting mixed immunization on an animal with the immunogenic polypeptide. The polyclonal antibody can specifically recognize an endogenous protein BAZ1B_K426hy by enzyme-linked immunosorbent assay (ELISA)/Dot blot/Western blot, which is used for preparation of detection products for tumors and Williams syndrome.
    Type: Application
    Filed: April 14, 2023
    Publication date: July 11, 2024
    Applicants: Tangshan People's Hospital, North China University of Science and Technology, Tangshan Maternal And Child Health Hospital
    Inventors: Jingwu LI, Yufeng Li, Shuqing Wang, Jinghua Zhang, Jinghua Wu, Fen Hu, Yuan Yu, Yan Liu, Yuhui Li, Xuan Zheng