Patents by Inventor Yue Liang

Yue Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9252146
    Abstract: A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: February 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yue Liang, Dechao Guo, William K. Henson, Shreesh Narasimha, Yanfeng Wang
  • Publication number: 20150349089
    Abstract: In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.
    Type: Application
    Filed: August 7, 2015
    Publication date: December 3, 2015
    Inventors: Brian J. Greene, Yue Liang, Xiaojun Yu
  • Patent number: 9163330
    Abstract: The invention relates to bifunctional stapled or stitched peptides comprising a targeting domain, a linker moiety, and an effector domain, that can be used to tether, or to bring into close proximity, at least two cellular entities (e.g., proteins). Certain aspects relate to bifunctional stapled or stitched peptides that bind to an effector biomolecule through the effector domain and bind to a target biomolecule through the targeting domain. Polypeptides and/or polypeptide complexes that are tethered by the bifunctional stapled or stitched peptides of the invention, where the effector polypeptide bound to the effector domain of the bifunctional stapled or stitched peptide modifies or alters the target polypeptide bound to the targeting domain of the bifunctional peptide. Uses of the inventive bifunctional stapled or stitched peptides including methods for treatment of disease (e.g., cancer, inflammatory diseases) are also provided.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: October 20, 2015
    Assignee: President and Fellows of Harvard College
    Inventors: Gregory L. Verdine, Tom N. Grossmann, Raymond E. Moellering, Tsung-Han Johannes Yeh, Yue Rebecca Yue Liang, Youbean Oak
  • Patent number: 9164234
    Abstract: A method of coupling optical fibers containing cores or other structures that twist about the axis of one or both fibers. The fiber end faces are aligned axially to confront one another, and side view images of end regions of the fibers including the contained cores or structures are produced. For each fiber, a brightness profile of a side view image is obtained at an axially offset position from the fiber end face. One or both fibers are rotated about their axes until the brightness profiles for each fiber indicate certain cores or structures in the fibers are aligned. For each fiber, an additional amount of twist from the offset position to the fiber end face is determined. One or both fibers are rotated again to compensate for the additional twist in each fiber, so that the fibers are aligned optimally when coupled.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: October 20, 2015
    Assignee: OFS FITEL, LLC
    Inventors: Kenneth S Feder, Yue Liang
  • Publication number: 20150279692
    Abstract: A method including forming a structure including a plurality of semiconductor devices surrounded by a dielectric layer such that a top surface of the dielectric layer is substantially flush with a top surface of the plurality of semiconductor devices, depositing a thermal optimization layer above the structure, patterning the thermal optimization layer such that a portion of the thermal optimization layer is removed from a above first region of the structure and another portion of the thermal optimization layer remains above a second region of the structure, the first region having a different thermal conductivity than the second region, and heating the structure, the patterned thermal optimization layer causing substantially uniform thermal absorption of the structure.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian J. Greene, Yue Liang, Xiaojun Yu
  • Patent number: 9109978
    Abstract: A light hood for a fiber identifier tool that includes a head portion having interior photo detectors, a slot for receiving an optical fiber to be tested, and a clamp mechanism for urging the fiber to bend in the vicinity of the photo detectors when the mechanism is operated. The hood has a generally T-shaped body that defines a lower hood portion arranged to engage the clamp mechanism and operate the mechanism when the lower hood portion is pulled downward by a user. An upper hood portion of the body is configured so that when the lower hood portion is engaged with the clamp mechanism and pulled downward, the upper hood portion descends to cover the head portion of the tool including the slot. Outside light is then blocked from entering the slot and reaching the photo detectors whenever a fiber is tested by the tool, thus preventing false indications.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: August 18, 2015
    Assignee: OFS FITEL, LLC
    Inventors: Yue Liang, Denis E. Burek
  • Publication number: 20150225471
    Abstract: Provided herein are stapled or stitched polypeptides comprising an alpha-helical segment, wherein the polypeptide binds to the insulin receptor, and wherein the polypeptide comprises at least two cross-linked amino acids as shown in Formula (iii), or at least three cross-linked amino acids as shown in Formula (iv). Further provided are pharmaceutical compositions comprising the stapled or stitched polypeptides, methods of use, e.g., methods of treating a diabetic condition or complications thereof. Precursor “unstapled” polypeptides useful in the preparation of stapled and stitched polypeptides are also described.
    Type: Application
    Filed: October 1, 2013
    Publication date: August 13, 2015
    Applicant: President and Fellows of Harvard College
    Inventors: Rebecca Yue Liang, Minyun Zhou, Gregory L. Verdine
  • Patent number: 9105722
    Abstract: In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Greene, Yue Liang, Xiaojun Yu
  • Patent number: 9082877
    Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
  • Patent number: 9040399
    Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
  • Patent number: 8993389
    Abstract: A method of forming a semiconductor device comprising a dummy gate interconnect includes forming a dummy gate on a substrate, the dummy gate comprising a dummy gate metal layer located on the substrate, and a dummy gate polysilicon layer located on the dummy gate metal layer; forming an active gate on the substrate, the active gate comprising an active gate metal layer located on the substrate, and an active gate polysilicon layer located on the active gate metal layer; and etching the dummy gate polysilicon layer to remove at least a portion of the dummy gate polysilicon layer to form the dummy gate interconnect, wherein the active gate polysilicon layer is not etched during the etching of the dummy gate polysilicon layer.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Greene, Yue Liang, Xiaojun Yu
  • Patent number: 8976344
    Abstract: A live fiber identifier tool includes a head portion having a slot. A cable containing a pair of optical fibers can be inserted in the slot and forced to bend inside the head portion when a trigger is operated. Any light signal in a given fiber partially leaks from the fiber and exits the cable bend. Two photo detectors are located so that one of the detectors receives more light from the cable bend than the other detector depending on the signal direction in the given fiber. Processing components coupled to the detectors and the indicator define a threshold factor that corresponds to a determined difference between the outputs of the detectors. If the difference between the detector outputs does not exceed the threshold factor, an indicator on the tool reports that light signals are traveling in the pair of optical fibers in opposite directions along the cable.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: March 10, 2015
    Assignee: OFS Fitel, LLC
    Inventors: Yue Liang, Ryuji Takaoka
  • Patent number: 8962417
    Abstract: A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source/drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kern Rim, William K. Henson, Yue Liang, Xinlin Wang
  • Publication number: 20150001585
    Abstract: In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 1, 2015
    Inventors: Brian J. Greene, Yue Liang, Xiaojun Yu
  • Publication number: 20140349451
    Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
    Type: Application
    Filed: May 30, 2014
    Publication date: November 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
  • Publication number: 20140307251
    Abstract: A live fiber identifier tool includes a head portion having a slot. A cable containing a pair of optical fibers can be inserted in the slot and forced to bend inside the head portion when a trigger is operated. Any light signal in a given fiber partially leaks from the fiber and exits the cable bend. Two photo detectors are located so that one of the detectors receives more light from the cable bend than the other detector depending on the signal direction in the given fiber. Processing components coupled to the detectors and the indicator define a threshold factor that corresponds to a determined difference between the outputs of the detectors. If the difference between the detector outputs does not exceed the threshold factor, an indicator on the tool reports that light signals are traveling in the pair of optical fibers in opposite directions along the cable.
    Type: Application
    Filed: April 16, 2013
    Publication date: October 16, 2014
    Applicant: OFS FITEL, LLC
    Inventors: Yue Liang, Ryuji Takaoka
  • Publication number: 20140307250
    Abstract: A light hood for a fiber identifier tool that includes a head portion having interior photo detectors, a slot for receiving an optical fiber to be tested, and a clamp mechanism for urging the fiber to bend in the vicinity of the photo detectors when the mechanism is operated. The hood has a generally T-shaped body that defines a lower hood portion arranged to engage the clamp mechanism and operate the mechanism when the lower hood portion is pulled downward by a user. An upper hood portion of the body is configured so that when the lower hood portion is engaged with the clamp mechanism and pulled downward, the upper hood portion descends to cover the head portion of the tool including the slot. Outside light is then blocked from entering the slot and reaching the photo detectors whenever a fiber is tested by the tool, thus preventing false indications.
    Type: Application
    Filed: April 12, 2013
    Publication date: October 16, 2014
    Applicant: OFS Fitel, LLC
    Inventors: Yue Liang, Denis E. Burek
  • Patent number: 8853035
    Abstract: In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xiaojun Yu, Brian J. Greene, Yue Liang
  • Publication number: 20140294350
    Abstract: A multicore fiber alignment apparatus is described, having a chassis into which is mounted ferrule-holding means for holding a multicore fiber ferrule having one or more capillaries extending therethrough. Fiber-holding means for holding one or more multicore fibers in position to be mounted into the ferrule, such that each multicore fiber extends through a respective ferrule capillary. Means are provided for monitoring the rotation angle of each multicore fiber within its respective capillary, relative to a reference rotational orientation. Means are further provided for rotating each of the multicore fibers within its respective capillary. The rotational orientation of each multicore fiber is fixed when its rotation angle is equal to zero.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 2, 2014
    Applicant: OFS Fitel, LLC
    Inventors: Kelvin B. Bradley, Wladyslaw Czosnowski, Tristan Kremp, Yue Liang
  • Publication number: 20140273381
    Abstract: A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source/drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kern Rim, William K. Henson, Yue Liang, Xinlin Wang