Abstract: A computer-implemented method, system and computer program product for improving accuracy of a vision model. Images of an object with a first set of perspectives are received from a dataset used to train the vision model. A three-dimensional model of the object is then generated using the images of the object from the dataset. Using the three-dimensional model of the object, images of the object with a second set of perspectives are obtained. For example, the second set of perspectives may include different perspectives than the perspectives of the object from the images contained in the dataset. The dataset used to train the vision model may then be augmented with such images of the object with a second set of perspectives. In this manner, the dataset used to train the vision model includes a greater number of perspectives of the object thereby improving the accuracy of the vision model.

Abstract: Embodiments of a three-dimensional (3D) memory device and a method of operating the 3D memory device are provided. The 3D memory device includes an array of 3D NAND memory cells, an array of static random-access memory (SRAM) cells, and a peripheral circuit. The array of SRAM cells and the peripheral circuit arranged at one side are bonded with the array of 3D NAND memory cells at another side to form a chip. Data is received from a host through the peripheral circuit, buffered in the array of SRAM cells, and transmitted from the array of SRAM cells to the array of 3D NAND memory cells. The data is programmed into the array of 3D NAND memory cells.

Abstract: Techniques for modeling subterranean characteristics by combining physical and numerical simulations using limited amounts of subsurface full diameter core samples via orthogonal experimentation schemes. Systems and methods applying synchronous fitting and prediction of physical simulation and numerical simulation to obtain the equivalent permeability of fracture cells in numerical simulation, to provide a basis for assigning a value to the equivalent fracture cell permeability during numerical simulation. According to the specific subterranean reservoir characteristics, the water invasion orthogonal experiments are completed by combining physical simulation with numerical simulation to analyze the main factors of water invasion in reservoirs.

Abstract: Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In certain embodiments, the 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes an array of SRAM cells and a first bonding layer, and the second semiconductor structure includes an array of 3D NAND memory strings and a second bonding layer. The first semiconductor structure is attached with the second semiconductor structure through the first bonding layer and the second bonding layer. The array of 3D NAND memory strings and the array of SRAM cells are coupled through a plurality of bonding contacts in the first bonding layer and the second bonding layer and are arranged at opposite sides of the plurality of bonding contacts.

Abstract: A three-dimensional (3D) memory device includes a 3D NAND memory array, an on-die static random-access memory (SRAM), and peripheral circuits formed on the same chip with the on-die SRAM. The peripheral circuits include a page buffer coupled to the on-die SRAM and a controller coupled to the on-die SRAM and the page buffer. The controller may be configured to load program data into the page buffer and cache the program data into the on-die SRAM as a backup copy of the program data. In response to a status of programming the program data from the page buffer into the 3D NAND memory array being failed, the controller may be further configured to transmit the backup copy of the program data in the on-die SRAM to the page buffer, and program the backup copy of the program data in the page buffer into the 3D NAND memory array.

Abstract: Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N?2)th batch of program data, N being an integer equal to or greater than 2, program an (N?1)th batch of program data into respective pages in the 3D NAND memory array, and cache an Nth batch of program data in respective space in the on-die cache as a backup copy of the Nth batch of program data.

Abstract: Embodiments of a three-dimensional (3D) memory device and a method of operating the 3D memory device are provided. The 3D memory device includes an array of 3D NAND memory cells, an array of static random-access memory (SRAM) cells, and a peripheral circuit. The array of SRAM cells and the peripheral circuit arranged at one side are bonded with the array of 3D NAND memory cells at another side to form a chip. Data is received from a host through the peripheral circuit, buffered in the array of SRAM cells, and transmitted from the array of SRAM cells to the array of 3D NAND memory cells. The data is programmed into the array of 3D NAND memory cells.

Abstract: Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In certain embodiments, the 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes an array of SRAM cells and a first bonding layer, and the second semiconductor structure includes an array of 3D NAND memory strings and a second bonding layer. The first semiconductor structure is attached with the second semiconductor structure through the first bonding layer and the second bonding layer. The array of 3D NAND memory strings and the array of SRAM cells are coupled through a plurality of bonding contacts in the first bonding layer and the second bonding layer and are arranged at opposite sides of the plurality of bonding contacts.

Abstract: An offline mode user account authorization method includes obtaining an access privilege of a user account and setting an offline task access privilege of the user account according to the access privilege, retrieving user account information corresponding to a task to be executed from a preset task information comparison table when the task to be executed is implemented, determining whether the user account is online, executing the task to be executed with a user ID of the user account if the user account is online, and creating a super offline user account and assigning offline task access privilege of the user account to the super offline user account if the user account is not online. The implemented task to be executed is executed with the super offline user account.

Abstract: Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages and an on-die data buffer coupled to the memory array on a same chip and configured to buffer a plurality of batches of program data between a host and the memory array. The on-die data buffer may include SRAM cells. The 3D memory device also includes a controller coupled to the on-die data buffer on the same chip. The controller may be configured to receive control instructions for performing a first pass program and a second pass program on memory cells in a page. The controller may also be configured to buffer, in the on-die data buffer, first program data for a first pass program and second program data for a second pass program from a host and retrieve the first program data from the on-die data buffer.

Abstract: Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In one example, the method for operating a 3D memory device having an input/output circuit, an array of SRAM cells, and an array of 3D NAND memory strings in a same chip. The method may include transferring data through the input/output circuit to the array of SRAM cells, storing the data in the array of SRAM cells, and programming the data into the array of 3D NAND memory strings from the array of SRAM cells.

Abstract: Techniques for modeling subterranean characteristics by combining physical and numerical simulations using limited amounts of subsurface full diameter core samples via orthogonal experimentation schemes. Systems and methods applying synchronous fitting and prediction of physical simulation and numerical simulation to obtain the equivalent permeability of fracture cells in numerical simulation, to provide a basis for assigning a value to the equivalent fracture cell permeability during numerical simulation. According to the specific subterranean reservoir characteristics, the water invasion orthogonal experiments are completed by combining physical simulation with numerical simulation to analyze the main factors of water invasion in reservoirs.

Abstract: Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In one example, the method for operating a 3D memory device having an input/output circuit, an array of SRAM cells, and an array of 3D NAND memory strings in a same chip. The method may include transferring data through the input/output circuit to the array of SRAM cells, storing the data in the array of SRAM cells, and programming the data into the array of 3D NAND memory strings from the array of SRAM cells.

Abstract: Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N?2)th batch of program data, N being an integer equal to or greater than 2, program an (N?1)th batch of program data into respective pages in the 3D NAND memory array, and cache an Nth batch of program data in respective space in the on-die cache as a backup copy of the Nth batch of program data.

Abstract: Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages and an on-die data buffer coupled to the memory array on a same chip and configured to buffer a plurality of batches of program data between a host and the memory array. The on-die data buffer may include SRAM cells. The 3D memory device also includes a controller coupled to the on-die data buffer on the same chip. The controller may be configured to receive control instructions for performing a first pass program and a second pass program on memory cells in a page. The controller may also be configured to buffer, in the on-die data buffer, first program data for a first pass program and second program data for a second pass program from a host and retrieve the first program data from the on-die data buffer.

Abstract: Embodiments of three-dimensional (3D) memory devices with a 3D memory device includes a first semiconductor structure having a peripheral circuit, an array of SRAM cells, and a first bonding layer having a plurality of first bonding contacts. The 3D memory device also includes a second semiconductor structure having an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts and a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: An offline mode user account authorization method includes obtaining an access privilege of a user account and setting an offline task access privilege of the user account according to the access privilege, retrieving user account information corresponding to a task to be executed from a preset task information comparison table when the task to be executed is implemented, determining whether the user account is online, executing the task to be executed with a user ID of the user account if the user account is online, and creating a super offline user account and assigning offline task access privilege of the user account to the super offline user account if the user account is not online. The implemented task to be executed is executed with the super offline user account.

Abstract: Various embodiments provide a single pole single throw switch. The switch may include a first terminal, a second terminal and a control terminal; a field-effect transistor having a drain connected to the first terminal, a source connected to the ground, and a gate; a bias resistor connected between the gate of the field-effect transistor and the control terminal; an inductor connected between the first terminal and the second terminal; and a capacitor having one end connected to the second terminal and another end connected to the ground.

Abstract: The present invention discloses a photo kiosk device. The photo kiosk device may include a housing with an extendable arm to provide a photo taking environment, a digital lens provided at one side of the housing to capture a photo image, a user interface provided at one side of the housing to display the captured photo image; and a photo slot provided at one side of the housing to output a finished photo product of the captured photo image, wherein the extendable arm, when extended, is provided with a back light source at a surface thereof to enhance a brightness of the photo taking environment.

Abstract: A switch for controlling signal propagation between a first and second contact is proposed. This switch comprises a control mechanism configured to allow signal propagation between the first and second contacts when the switch is turned on and prevent signal propagation between the first and second contacts when the switch is turned off. The switch also comprises a compensating member having a transmission line and a ground plane. The ground plane in turn comprises at least one defect configured to affect one or both of the inductance and capacitance of the transmission line when signals propagate through the transmission line.