Abstract: A low noise amplifier circuit including a front end voltage sensing and matching amplification circuit, a gain circuit and a combining circuit is disclosed. The front end voltage sensing and matching amplification circuit includes an input and two outputs and provides a matched signal at each output. The gain circuit includes two inputs, each input being respectively coupled to at least one of the two outputs of the front end voltage sensing and matching amplification circuit. The gain circuit further includes two outputs and an output signal is provided at each output of the gain circuit. The combining circuit combines the two output signals of the gain circuit. The combining circuit includes two inputs, each input is respectively coupled to at least one of the two outputs of the gain circuit. The combining circuit further includes an output providing a combined signal.

Abstract: An airflow guider includes a plate-like member having a stop portion extending transversely, a rear inclined guiding portion extending downward rearward toward a first side from a top edge of the stop portion, a front inclined guiding portion extending slantwise forward toward the first side from the stop portion, and at least one fixture for installing the airflow guider to a heat sink. In light of the structure, the airflow guider can be coordinately installed to various kinds of heat sinks and provide additional thermal dissipation.

Abstract: An integrated circuit structure is disclosed. The integrated circuit structure includes a first package substrate including a radiating element, the radiating element having a radiating element connection extending from the radiating element. The integrated circuit structure further includes a first chip positioned adjacent to the radiating element connection, the first chip having a first chip connection on a surface of the first chip, wherein the first chip connection forms a capacitive coupling with the radiating element connection. A method of forming an integrated circuit structure is also disclosed.

Abstract: A heat-dissipating fin includes a sheety main body. The main body is provided with a high-temperature area located at each of two sides thereof, an airflow area located at a midsection thereof for an external airflow to pass through, at least one guide wall formed at the airflow area and having a front end facing the main body, and two inclined guide portions each extending rearward toward one side thereof from a front end thereof. In this way, the external airflow can be guided to the high-temperature areas of the fin to reach greater heat-dissipating efficiency.

Abstract: A battery cover includes an outer panel, an inner panel, a resilient member and a chassis. The inner panel is disposed on the outer panel. The resilient member is located on the inner panel and includes two elongated arms. Each elongated arm includes a contact at the distal end thereof. The chassis is disposed on the resilient member and the inner panel, and is fastened to the outer panel. The chassis defines two openings configured for the two contacts to extend out correspondingly.

Abstract: A transistor arrangement including a triple well structure, the triple well structure including a substrate of a first conductivity type, a first well region of a second conductivity type formed within the substrate and a second well region of the first conductivity type being separated from the substrate by the first well region. The transistor arrangement further includes a first transistor formed on or in the second well region, the first transistor including a body terminal being connected to the second well region and a second well region switch being connected to the body terminal of the first transistor.

Abstract: A chip arrangement is disclosed. The chip arrangement includes a first chip, a first bond wire having an inductive element and coupled with the first chip at its one end and an inductivity compensation structure including a first conductive plate coupled with the first bond wire at the other end of the first bond wire, and a second conductive plate arranged in parallel to the first conductive plate, wherein the first conductive plate and the second conductive plate are configured such that a resonant condition for a partial circuit formed by the first bond wire and the inductivity compensation structure is formed to compensate for the inductive element of the first bond wire. A method of determining an inductivity compensation structure for compensating a bond wire inductivity in a chip arrangement is also disclosed.

Abstract: A housing (100) of a portable electronic device includes an opaque base (10) and a transparent cover (20). The base defines an aperture (101). The cover is fixed on the base by means of laser soldering and covers the aperture. A method for fabricating the housing is also described.

Abstract: A device package for radio frequency transceivers that comprises radio electronics, a filter and an antenna. The filter and antenna are realized using one or more metallization layers in the housing of the device package. The filter and antenna in the housing of the device package allows the realization of a compact RF transceiver with a small form-factor.

Abstract: An antenna on a substrate, the antenna being symmetrical about a central longitudinal axis of symmetry, the antenna comprising a first portion that is substantially rectangular, a second portion that is substantially rectangular, the first portion and the second portion being spaced from each other and being operatively connected by an intermediate portion.

Abstract: A method and implementation for communicating between logic functions using non-metallic coupling between logic functions on a same chip or separate chip is shown. For communication on the same chip, radiated energy from an antenna coupled to a transmitting logic function is coupled to a receiving antenna and then coupled by an electrical connection to a receiving logic function. Communication between USLI chips mounted on a module is performed by coupling an RF signal from a first chip to a ?-satellite mounted within the module and then coupling the RF signal from the satellite to a second chip. Communication can also be formed between the satellite and different logical functions on the same USLI chip.