Patents by Inventor Yueh-Ching Pai
Yueh-Ching Pai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10872769Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: GrantFiled: December 30, 2019Date of Patent: December 22, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Publication number: 20200303378Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Inventors: Chun-Chieh Wang, Yueh-Ching Pai, Huai-Tei Yang
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Patent number: 10752995Abstract: A method includes applying a first amount of heat to a vapor region of a precursor canister, measuring an indication of saturated vapor pressure within the vapor region during the applying the first amount of heat, and applying a second amount of heat to the vapor region of the precursor canister, the second amount of heat being adjusted from the first amount of heat based on the indication of saturated vapor pressure.Type: GrantFiled: February 24, 2017Date of Patent: August 25, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Chih Liu, Chia-Ming Tsai, Yen-Yu Chen, Yueh-Ching Pai, Yu-Min Chang
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Publication number: 20200251574Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.Type: ApplicationFiled: April 20, 2020Publication date: August 6, 2020Inventors: Chien-Shun Liao, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chun-I Wu
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Patent number: 10679995Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.Type: GrantFiled: February 14, 2019Date of Patent: June 9, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Wang, Yueh-Ching Pai, Huai-Tei Yang
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Publication number: 20200135471Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: ApplicationFiled: December 30, 2019Publication date: April 30, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
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Publication number: 20200126797Abstract: A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.Type: ApplicationFiled: March 1, 2019Publication date: April 23, 2020Inventors: Chun-Chieh Wang, Kuo-Jung Huang, Yueh-Ching Pai, Huai-Tei Yang
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Patent number: 10629700Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.Type: GrantFiled: September 28, 2018Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Shun Liao, Huai-Tei Yang, Wang Chun-Chieh, Yueh-Ching Pai, Chun-I Wu
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Publication number: 20200105532Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Chien-Shun Liao, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chun-I Wu
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Publication number: 20200075407Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.Type: ApplicationFiled: November 8, 2019Publication date: March 5, 2020Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chen-Yuan Kao, Yi-Wei Chiu, Liang-Yueh Ou Yang, Yueh-Ching Pai
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Publication number: 20200052126Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.Type: ApplicationFiled: October 16, 2019Publication date: February 13, 2020Inventors: Chun-Chieh WANG, Yu-Ting LIN, Yueh-Ching PAI, Shih-Chieh CHANG, Huai-Tei YANG
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Publication number: 20200043927Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.Type: ApplicationFiled: February 14, 2019Publication date: February 6, 2020Inventors: Chun-Chieh Wang, Yueh-Ching Pai, Huai-Tei Yang
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Patent number: 10535523Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: GrantFiled: August 30, 2018Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Patent number: 10483165Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.Type: GrantFiled: December 7, 2018Date of Patent: November 19, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chen-Yuan Kao, Yi-Wei Chiu, Liang-Yueh Ou Yang, Yueh-Ching Pai
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Patent number: 10468530Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer and a source/drain structure. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The source/drain structure includes a first source/drain epitaxial layer and a second source/drain epitaxial layer. The first source/drain epitaxial layer is in contact with the fin structure. The first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure. The lattice constant of the first source/drain epitaxial layer is different from the lattice constant of the second source/drain epitaxial layer.Type: GrantFiled: July 24, 2018Date of Patent: November 5, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
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Patent number: 10332789Abstract: The present disclosure relates generally to techniques for forming a continuous adhesion layer for a contact plug. A method includes forming an opening through a dielectric layer to an active area on a substrate. The method includes performing a first plasma treatment along a sidewall of the opening. The method includes performing an atomic layer deposition (ALD) process to form a metal nitride layer along the sidewall of the opening. The ALD process includes a plurality of cycles. Each cycle includes flowing a precursor to form a metal monolayer along the sidewall and performing a second plasma treatment to treat the metal monolayer with nitrogen. The method includes depositing a conductive material on the metal nitride layer in the opening to form a conductive feature.Type: GrantFiled: February 2, 2018Date of Patent: June 25, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Pei Chou, Ken-Yu Chang, Chun-Chieh Wang, Yueh-Ching Pai, Yu-Ting Lin, Yu-Wen Cheng
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Publication number: 20190164822Abstract: The present disclosure relates generally to techniques for forming a continuous adhesion layer for a contact plug. A method includes forming an opening through a dielectric layer to an active area on a substrate. The method includes performing a first plasma treatment along a sidewall of the opening. The method includes performing an atomic layer deposition (ALD) process to form a metal nitride layer along the sidewall of the opening. The ALD process includes a plurality of cycles. Each cycle includes flowing a precursor to form a metal monolayer along the sidewall and performing a second plasma treatment to treat the metal monolayer with nitrogen. The method includes depositing a conductive material on the metal nitride layer in the opening to form a conductive feature.Type: ApplicationFiled: February 2, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Pei CHOU, Ken-Yu CHANG, Chun-Chieh WANG, Yueh-Ching PAI, Yu-Ting LIN, Yu-Wen CHENG
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Publication number: 20190148223Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.Type: ApplicationFiled: April 30, 2018Publication date: May 16, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Pei CHOU, Ken-Yu CHANG, Sheng-Hsuan LIN, Yueh-Ching PAI, Yu-Ting LIN
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Publication number: 20190148556Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer and a source/drain structure. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The source/drain structure includes a first source/drain epitaxial layer and a second source/drain epitaxial layer. The first source/drain epitaxial layer is in contact with the fin structure. The first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure. The lattice constant of the first source/drain epitaxial layer is different from the lattice constant of the second source/drain epitaxial layer.Type: ApplicationFiled: July 24, 2018Publication date: May 16, 2019Inventors: Chun-Chieh WANG, Yu-Ting LIN, Yueh-Ching PAI, Shih-Chieh CHANG, Huai-Tei YANG
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Publication number: 20190115256Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.Type: ApplicationFiled: December 7, 2018Publication date: April 18, 2019Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chen-Yuan Kao, Yi-Wei Chiu, Liang-Yueh Ou Yang, Yueh-Ching Pai