Abstract: An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV.

Abstract: A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, a plurality of first interconnect structures, right above the TSV, configured for electrically coupling the TSV to a higher-level interconnect, a second interconnect structure traversing the TSV from the top and being configured for interconnect routing of an active device and a plurality of dummy metal patterns, right above the TSV, electrically isolated from the TSV, the first interconnect structures and the second interconnect structure.

Abstract: A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.

Abstract: A method for fabricating a through-silicon via comprises the following steps. Provide a substrate. Form a through silicon hole in the substrate having a diameter of at least 1 ?m and a depth of at least 5 ?m. Perform a first chemical vapor deposition process with a first etching/deposition ratio to form a dielectric layer lining the bottom and sidewall of the through silicon hole and the top surface of the substrate. Perform a shape redressing treatment with a second etching/deposition ratio to change the profile of the dielectric layer. Repeat the first chemical vapor deposition process and the shape redressing treatment at least once until the thickness of the dielectric layer reaches to a predetermined value.

Abstract: A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, at least one first interconnect structure traversing the TSV from the top and dividing a region right above the TSV into several sub-regions and being configured for interconnect routing of an active device and a plurality of second interconnect structures occupying the sub-regions right above the TSV and being configured for electrically coupling the TSV to a higher-level interconnect.

Abstract: A stacked integrated circuit system comprises a first chip with first average pattern density comprising memory cells, a second chip with second average pattern density comprising logic circuitries for the memory cells and a functioning unit and a plurality of through-silicon vias within one of the first chip and second chip to electrically connect the first chip and the second chip, wherein the memory cells of the first chip and the logic circuitries of the second chip are designed to be used collectively in order to perform complete memory functions, and wherein the first average pattern density is higher than the second average pattern density.

Abstract: A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.

Abstract: A semiconductor device comprises a substrate having a first side with a first surface and a second side with a second surface, a recessed through silicon via (TSV) penetrating the substrate and forming a first step height with respect to the first surface of the first side, a first extruded backside redistribution line (RDL) filling in the first step height and engaging with the recessed through silicon via.

Abstract: A semiconductor device with a through-silicon via comprises a substrate with a front side and a backside and a through-silicon via penetrating the substrate with a circular shape on the front side and a corner-rounded rectangular shape on the back side.

Abstract: An integrated structure comprises a substrate with a first dielectric layer and a second dielectric cap layer disposed thereon in sequence, a metal gate transistor with a high-k gate dielectric layer on the substrate, a gate electrode embedded within the first dielectric layer and a source/drain within the substrate, a first metal contact penetrating the first dielectric layer and being in direct contact with the source/drain and a through-silicon via penetrating the second dielectric cap layer, the first dielectric layer and the substrate.

Abstract: A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, a plurality of first interconnect structures, right above the TSV, configured for electrically coupling the TSV to a higher-level interconnect, a second interconnect structure traversing the TSV from the top and being configured for interconnect routing of an active device and a plurality of dummy metal patterns, right above the TSV, electrically isolated from the TSV, the first interconnect structures and the second interconnect structure.

Abstract: A method for fabricating a through-silicon via comprises the following steps. Provide a substrate. Form a through silicon hole in the substrate having a diameter of at least 1 ?m and a depth of at least 5 ?m. Perform a first chemical vapor deposition process with a first etching/deposition ratio to form a dielectric layer lining the bottom and sidewall of the through silicon hole and the top surface of the substrate. Perform a shape redressing treatment with a second etching/deposition ratio to change the profile of the dielectric layer. Repeat the first chemical vapor deposition process and the shape redressing treatment at least once until the thickness of the dielectric layer reaches to a predetermined value.

Abstract: An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV.

Abstract: First of all, a semiconductor substrate that has a gate dielectric layer thereon is provided. Then a polysilicon layer is formed on the gate dielectric layer. Next, a dielectric layer having a first thickness is formed on the polysilicon layer. Afterward, form and define a photoresist layer on the dielectric layer. The dielectric layer is then etched by way of using the photoresist layer as an etching mask and a mixing gas that comprises a C2F6 and a CH2F2 as an etchant until the polysilicon layer is over etched to consume a second thickness, so as to form a hard mask with a trapezoid profile, wherein the second thickness is about half of the first thickness. After removing the photoresist layer, the polysilicon layer is etched by way of using the hard mask as an etching mask to form a poly-gate.

Abstract: First of all, a semiconductor substrate is provided, the semiconductor substrate has a dielectric layer thereon. Then a photoresist layer is formed and defined on the dielectric layer. Next, an etching process is performed by the photoresist layer as an etched mask to form a trench in the dielectric layer, wherein the etchant of the etching process comprises a mixing gas with a C4F6 gas or a CH2F2 gas, such as C4F6/CH2F2/Ar/O2 or C4F6/CH2F2/Ar/O2/CF4 or C4F6/CH2F2/Ar/O2/C2F6, accordingly, the etching capability of the etchant and the etching selectivity between the dielectric layer and the photoresist layer can be raised. Finally, the photoresist layer is removed to form the contact window or the via hole with high accurate critical dimension.

Abstract: A polymer debris pre-cleaning method is described. The method provides a specific gas mixture after an etching process that uses a fluorocarbon reacting gas. The plasma generated from the gas mixture is then used to perform a pre-cleaning of the polymer debris. The gas mixture of specific gases is selected from the group of an oxygen and nitrogen gas mixture, a hydrogen and argon gas mixture, an argon and nitrogen gas mixture, or an oxygen and argon gas mixture. Since the plasma generated from the gas mixture softens, burns or even removes the hardened polymer debris, the polymer debris can be completely removed in the subsequent cleaning process. The duration of the subsequent cleaning process is thus reduced.

Abstract: A metal etching process. A glue/barrier layer, a metal layer and an anti-refeletion layer are formed on a substrate. A three-stage etching step is performed. A break through step of etching is performed to pattern the glue/barrier layer. A main etching step is performed on the metal layer with chlorine, boron trichloride, and trifluoro-methane as etching gases. The trifluoro-methane is advantageous to produce a polymer during etching, so that the profile of the metal layer appears atilt. An over-etching step is then performed to ensure an insulation between neighboring wiring lines.

Abstract: A metal etching process. A glue/barrier layer, a metal layer and an anti-refeletion layer are formed on a substrate. A three-stage etching step is performed. A break through step of etching is performed to pattern the glue/barrier layer. A main etching step is performed on the metal layer with chlorine, boron trichloride, and trifluoro-methane as etching gases. The trifluoro-methane is advantageous to produce a polymer during etching, so that the profile of the metal layer appears atilt. An over-etching step is then performed to ensure an insulation between neighboring wiring lines.

Abstract: A method of forming a dual damascene structure. A first dielectric layer is formed over a substrate, and then the first dielectric layer is planarized. The first dielectric layer is etched to form a dual damascene opening that includes a via opening and a trench. The via opening exposes a conductive layer in the substrate. A metallic is formed in the via openings and the trenches so that a metallic interconnect and a via are formed at the same time. A cap layer is formed on the metallic layer. An additional etching stop layer may form on the cap layer and the substrate. A second dielectric layer is formed over the substrate. The second dielectric layer is etched to form a via opening that exposes a portion of the cap layer.

Abstract: A method for forming a via hole provides a substrate, and a conducting layer is formed on the substrate. An intermetal dielectric layer is deposited conformal to the substrate, and a patterned photoresist is formed on the intermetal dielectric layer. The photoresist is used as a mask, and a portion of intermetal dielectric layer, which is not covered by the photoresist, is removed to expose the conducting layer, so that an opening is formed. A polymer layer is unavoidably formed on the surface of the opening, and then the photoresist and the polymer layer are removed. The residual polymer layer is removed by wet bench to form a via hole.