Patents by Inventor Yueh-Feng Ho

Yueh-Feng Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6133143
    Abstract: The invention provides a method of manufacturing a metal interconnect. A substrate having a metal line formed thereon is provided. An anti-reflection layer is formed on the metal line. A dielectric layer with a relatively low dielectric constant is formed over the substrate. A patterned photoresist layer is formed on the dielectric layer. The patterned photoresist layer has an opening exposing a portion of the dielectric layer. The portion of the dielectric layer exposed by the opening is removed to form a via hole. The patterned photoresist layer is removed by an O.sub.2 --H.sub.2 O--CF.sub.4 plasma. The pressure of the O.sub.2 --H.sub.2 O--CF.sub.4 plasma is about 800-1000 torr. A cleaning process is performed by a post-stripper rinse solution and de-ionized water without using an acetone solution. A barrier layer is formed over the substrate by chemical vapor deposition. A metal nucleation is performed for a long time by chemical vapor deposition to form metal nuclei on the barrier layer.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: October 17, 2000
    Assignees: United Semiconductor Corp., United Microelectronics Corp.
    Inventors: Jy-Hwang Lin, Ching-Hsing Hsieh, Yueh-Feng Ho, Chia-Chieh Yu
  • Patent number: 6083825
    Abstract: An improved method of fabricating an unlanded via hole on a semiconductor substrate is provided. A conductive line and a patterned anti-reflection coating layer are sequentially formed on the substrate wherein the patterned anti-reflection coating layer has a smaller width than the conductive line and a portion of the conductive layer is exposed by the patterned anti-reflection coating layer. A planarized dielectric layer is formed over the substrate to cover the patterned anti-reflection coating layer and the conductive line. A via hole is formed in the planarized dielectric layer to expose portions of surface and sidewalls of the patterned anti-reflection coating layer as well as the conductive line.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: July 4, 2000
    Assignee: United Semiconductor Corp.
    Inventors: Jy-Hwang Lin, Yueh-Feng Ho, Pei-Jen Wang
  • Patent number: 5882537
    Abstract: Disclosed is a method of etching which makes the quantitative analysis possible and easier. In the prior art, chemical plasma etching is mainly by ion bombardment, and the tool used to observe the metal bulk is transmission electron microscopy (TEM), so it is very difficult and complicated to execute quantitative analysis. By using chemical plasma etching, the metal precipitate will be left almost all at the end of etching. Scanning electron microscopy (SEM) is used instead of TEM to perform the quantitative analysis.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: March 16, 1999
    Assignee: United Microelectronic Corp.
    Inventors: Yueh-Feng Ho, Chia-Chieh Yu