Patents by Inventor Yueh-Se Ho

Yueh-Se Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200194347
    Abstract: A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 18, 2020
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Yan Xun Xue, Xiaotian Zhang, Long-Ching Wang, Yueh-Se Ho, Zhiqiang Niu
  • Publication number: 20200194395
    Abstract: A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 18, 2020
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Xiaotian Zhang, Yan Xun Xue, Long-Ching Wang, Yueh-Se Ho, Zhiqiang Niu
  • Patent number: 10573762
    Abstract: A nitride-based Schottky diode includes a nitride-based semiconductor body, a first metal layer forming the anode electrode, a cathode electrode in electrical contact with the nitride-based semiconductor body, and a termination structure including a guard ring and a dielectric field plate. In one embodiment, the cathode electrode is formed on the front side of the nitride-based semiconductor body, in an area away from the anode electrode and the termination structure. In another embodiment, the dielectric field plate includes a first dielectric layer and a recessed second dielectric layer. In another embodiment, the dielectric field plate and the nitride-based epitaxial layer are formed with a slant profile at a side facing the Schottky junction of the Schottky diode. In another embodiment, the dielectric field plate is formed on a top surface of the nitride-based epitaxial layer and recessed from an end of the nitride-based epitaxial layer near the Schottky junction.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: February 25, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Patent number: 10522666
    Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 31, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
  • Publication number: 20190296157
    Abstract: A nitride-based Schottky diode includes a nitride-based semiconductor body, a first metal layer forming the anode electrode, a cathode electrode in electrical contact with the nitride-based semiconductor body, and a termination structure including a guard ring and a dielectric field plate. In one embodiment, the cathode electrode is formed on the front side of the nitride-based semiconductor body, in an area away from the anode electrode and the termination structure. In another embodiment, the dielectric field plate includes a first dielectric layer and a recessed second dielectric layer. In another embodiment, the dielectric field plate and the nitride-based epitaxial layer are formed with a slant profile at a side facing the Schottky junction of the Schottky diode. In another embodiment, the dielectric field plate is formed on a top surface of the nitride-based epitaxial layer and recessed from an end of the nitride-based epitaxial layer near the Schottky junction.
    Type: Application
    Filed: April 29, 2019
    Publication date: September 26, 2019
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Patent number: 10333006
    Abstract: A method for forming a nitride-based Schottky diode includes forming a nitride-based epitaxial layer on a front side of a nitride-based semiconductor body; forming a first dielectric layer on the nitride-based epitaxial layer; etching the first dielectric layer and the nitride-based epitaxial layer to the nitride-based semiconductor body to define an opening for an anode electrode of the nitride-based Schottky diode and to form an array of islands of the nitride-based epitaxial layer in the opening, the first dielectric layer having an end that is recessed from an end of the nitride-based epitaxial layer near the opening. In another embodiment, the first dielectric layer and the nitride-based epitaxial layer have a slant profile at a side facing the opening for the anode electrode.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: June 25, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Publication number: 20190189569
    Abstract: A semiconductor wafer is singulated to form a plurality of semiconductor packages. The semiconductor wafer has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A semiconductor package has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A thickness of the rigid supporting layer is larger than a thickness of the semiconductor substrate. A thickness of the metal layer is thinner than the thickness of the semiconductor substrate. An entirety of the rigid supporting layer may be made of a single crystal silicon material or a poly-crystal silicon material. The single crystal silicon material or the poly-crystal silicon material may be fabricated from a reclaimed silicon wafer. An advantage of using a reclaimed silicon wafer is for a cost reduction.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 20, 2019
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Long-Ching Wang, Zhen Du, Bo Chen, Jun Lu, Yueh-Se Ho
  • Publication number: 20180323315
    Abstract: A method for forming a nitride-based Schottky diode includes forming a nitride-based epitaxial layer on a front side of a nitride-based semiconductor body; forming a first dielectric layer on the nitride-based epitaxial layer; etching the first dielectric layer and the nitride-based epitaxial layer to the nitride-based semiconductor body to define an opening for an anode electrode of the nitride-based Schottky diode and to form an array of islands of the nitride-based epitaxial layer in the opening, the first dielectric layer having an end that is recessed from an end of the nitride-based epitaxial layer near the opening. In another embodiment, the first dielectric layer and the nitride-based epitaxial layer have a slant profile at a side facing the opening for the anode electrode.
    Type: Application
    Filed: June 26, 2018
    Publication date: November 8, 2018
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Patent number: 10050134
    Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 14, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
  • Patent number: 10038106
    Abstract: A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 31, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Publication number: 20180204937
    Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 19, 2018
    Inventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
  • Patent number: 9929076
    Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: March 27, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yan Xun Xue, Yueh-Se Ho, Hamza Yilmaz, Jun Lu
  • Patent number: 9837386
    Abstract: A power conversion device including a low-side MOSFET, a high-side MOSFET and an integrated control IC chip is disclosed. The power conversion device further includes a substrate comprising a first mounting area having a first group of welding discs and a second mounting area having a second group of welding discs; a first chip flipped and attached to the first mounting area; a second chip flipped and attached to the second mounting area; a metal clip; and a molding body covering a front surface of the substrate, the first chip, the second chip and the metal clip. Metal pads on a front side of the first chip is attached to the first group of welding discs. Metal pads on a front side of the second chip is attached to the second group of welding discs. The metal clip connects a connection pad to a back metal layer of the first chip.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: December 5, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Xiaotian Zhang, Shekar Mallikarjunaswamy, Zhiqiang Niu, Cheow Khoon Oh, Yueh-Se Ho
  • Publication number: 20170301800
    Abstract: A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.
    Type: Application
    Filed: June 29, 2017
    Publication date: October 19, 2017
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Patent number: 9786583
    Abstract: A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first pin and the second pin are located near two adjacent corners of the plastic package body. The bottom surface and two side surfaces of each of the first pin and the second pin are exposed from the plastic package body. Locking mechanisms are constructed to prevent the first pin and the second pin from falling off the power semiconductor package device during a manufacturing cutting process. Portions of the first pin, portions of the second pin, and portions of the plastic package body can be cut off.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: October 10, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, De Mei Gong
  • Patent number: 9768146
    Abstract: The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 19, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Zhiqiang Niu, Yan Xun Xue, Man Sheng Hu, Jun Lu, Yueh-Se Ho, Hamza Yilmaz
  • Patent number: 9735094
    Abstract: A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: August 15, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yueh-Se Ho, Hamza Yilmaz, Yan Yun Xue, Jun Lu
  • Patent number: 9728655
    Abstract: A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: August 8, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Publication number: 20170200705
    Abstract: A power device including a low-side MOSFET, a high-side MOSFET and an integrated control IC chip is disclosed. The power device further includes a substrate comprising a first mounting area having a first group of welding discs and a second mounting area having a second group of welding discs; a first chip flipped and attached to the first mounting area; a second chip flipped and attached to the second mounting area; a metal clip; and a molding body covering a front surface of the substrate, the first chip, the second chip and the metal clip. Metal pads on a front side of the first chip is attached to the first group of welding discs. Metal pads on a front side of the second chip is attached to the second group of welding discs. The metal clip connects a connection pad to a back metal layer of the first chip.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 13, 2017
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Xiaotian Zhang, Shekar Mallikarjunaswamy, Zhiqiang Niu, Cheow Khoon Oh, Yueh-Se Ho
  • Patent number: 9685430
    Abstract: A method of manufacturing an embedded package comprises attaching a plurality of chips on a pre-mold lead frame; forming a first lamination layer on the plurality of chips, the pre-mold lead frame and a plurality of pins; forming a first plurality of vias and a second plurality of vias through the first lamination layer; forming a respective conductive plug of a plurality of conductive plugs by depositing a respective conductive material in each of the first plurality of vias and each of the second plurality of vias; and electrically connecting the plurality of conductive plugs on the electrodes of the plurality of chips to the plurality of conductive plugs on the plurality of pins.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: June 20, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Zhiqiang Niu, Hua Pan, Ming-Chen Lu, Yueh-Se Ho, Jun Lu