Abstract: A method of manufacturing a semiconductor structure includes forming a first dielectric layer surrounding an optical component. The method further includes forming a thermal control mechanism adjacent to the optical component and at least partially surrounded by the first dielectric layer. Forming the thermal control mechanism includes forming a first thermoelectric member having a first conductivity type, forming a second thermoelectric member having a second conductivity type opposite to the first conductivity type, wherein the second thermoelectric member is opposite to the first thermoelectric member; and forming a conductive structure over and electrically connected to the thermal control mechanism. The method further includes forming a second dielectric layer over the first dielectric layer and surrounding the conductive structure.

Abstract: A method of analyzing an integrated circuit (IC) is provided. An original netlist of the IC is obtained according to a layout and a schematic of the IC. A first simulation is performed with the original netlist to obtain electrical properties of devices in the IC. A thermal analysis is performed on the IC according to the electrical properties, to obtain a localized temperature parameter of each of the devices. A second simulation is performed according to the original netlist and the localized temperature parameter of each of the devices. The localized temperature parameter of each of the devices is determined according to a voltage and a current of the device during the first simulation.

Abstract: A method of making a semiconductor device includes defining an opening extending from a first side of a substrate to a second side of the substrate, wherein the first side of the substrate is opposite the second side of the substrate. The method further includes depositing a dielectric material into the opening, wherein the dielectric material has a first refractive index. The method further includes etching the dielectric material to define a core opening extending from the first side of the substrate to the second side of the substrate. The method further includes depositing a core material into the core opening, wherein the core material has a second refractive index different from the first refractive index, and the core material is optically transparent. The method further includes removing excess core material from a surface of the substrate.

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a bottom package having a first sidewall and a second sidewall opposite to each other; a hybrid path layer disposed on the bottom package, wherein the hybrid path layer comprises an optical path layer and an electrical path layer, and at least one optical path of the optical path layer extends from the first sidewall of the bottom package beyond a center of the bottom package; and a plurality of dies bonded onto the hybrid path layer.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A method for manufacturing an integrated circuit includes forming an active area in a substrate, forming a gate structure on the active area, depositing an insulating layer, etching electrical contact openings to the gate structure and the active area, depositing a first conductive composition in the electrical contact openings to form an electrical contact layer that partially fills the electrical contact openings, filling a remainder of the electrical contact openings to form a plurality of electrical contacts. The method includes etching thermal contact openings to the active area, depositing a second conductive composition in the thermal contact openings to form a thermal contact layer that partially fills the thermal contact openings, wherein the first conductive composition differs from the second conductive composition, filling a remainder of the thermal contact openings to form a plurality of thermal contacts, and thermally connecting the plurality of thermal contacts and a heat dissipation structure.

Abstract: A semiconductor device includes an integrated passive device coupled to a redistribution structure by a plurality of first bumps, and having a plurality of second bumps disposed opposite the plurality of first bumps, wherein the plurality of first and second bumps are thermally and/or electrically connected, and thus enable further thermal and/or electrical connections within or comprising the semiconductor device.

Abstract: A method of manufacturing a semiconductor structure includes forming a first dielectric layer surrounding an optical component. The method includes forming a thermal control mechanism adjacent to the optical component and at least partially surrounded by the first dielectric layer. Forming the thermal control mechanism includes forming a first thermoelectric member having a first conductivity type, forming a second thermoelectric member having a second conductivity type opposite to the first conductivity type, wherein the second thermoelectric member is opposite to the first thermoelectric member; and electrically connecting the first thermoelectric member to the second thermoelectric member.

Abstract: A method of making a semiconductor device includes defining an opening extending from a first side of a substrate to a second side of the substrate, wherein the first side of the substrate is opposite the second side of the substrate. The method further includes depositing a dielectric material into the opening, wherein the dielectric material has a first refractive index. The method further includes etching the dielectric material to define a core opening extending from the first side of the substrate to the second side of the substrate. The method further includes depositing a core material into the core opening, wherein the core material has a second refractive index different from the first refractive index, and the core material is optically transparent. The method further includes removing excess core material from a surface of the substrate.

Abstract: A probe card, a method for designing the probe card, a method for producing a tested semiconductor device, a method for testing an unpackaged semiconductor by the probe card, a device under test, and a probe system are provided. The probe card includes a wiring substrate, a connection carrier board, and a probe device. At least two probes electrically connected to a loopback path of the connection carrier board to form a test signal loopback path. The probe device has a probe device impedance on the test signal loopback path. The loopback path has a loopback line impedance on the test signal loopback path. A difference between the probe device impedance on the test signal loopback path and the loopback line impedance on the test signal loopback path is in an impedance range.

Abstract: The present invention discloses an air mattress system including a first protection cell group disposed on one side of a support cell group. The first protection cell group includes a first middle cell having a height not exceeding a support surface, so as to preserve smooth routing paths for medical treatment pipelines and prevent obstructed flow of fluids. A front and a rear of the first protection cell group are respectively provided with a first front cell and a first rear cell, both of which are provided with bottom air chambers. When a patient needs to be transferred, the bottom air chambers are controlled to be deflated so that tops of the first front cell and the first rear cell are substantially lowered to be near the support surface to provide the patient with an unobstructed transition during the transfer.

Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

Abstract: A semiconductor device includes an optical connector element and an optical coupler. The optical connector element includes a base structure, a first polymer via and a cladding layer. The base structure has a first surface and a second surface opposite to the first surface. The first polymer via passes through the base structure from the first surface to the second surface. The cladding layer is surrounding the first polymer via, wherein a refractive index of the cladding layer is different than a refractive index of the first polymer via. The optical coupler is disposed over the optical connector element, wherein the optical coupler receives optical signals from the first polymer via.

Abstract: A probe card, a method for designing the probe card, a method for producing a tested semiconductor device, a method for testing an unpackaged semiconductor by the probe card, a device under test, and a probe system are provided. The probe card includes a wiring substrate, a connection carrier board, and a probe device. At least two probes form a differential pair electrically connected to a loopback line of the connection carrier board to form a test signal loopback path. The probe device has a probe device impedance on the test signal loopback path. The loopback line has a loopback line impedance on the test signal loopback path. A difference between the probe device impedance on the test signal loopback path and the loopback line impedance on the test signal loopback path is in an impedance range.

Abstract: A semiconductor package includes a first integrated circuit, a first waveguide, a second integrated circuit and a first redistribution layer structure. The first integrated circuit includes an optical coupler. The first waveguide is optically coupled to the optical coupler. The second integrated circuit is electrically connected to the first integrated circuit through the first redistribution layer structure.

Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

Abstract: A semiconductor device includes an optical connector element and an optical coupler. The optical connector element includes a base structure, a first polymer via and a cladding layer. The base structure has a first surface and a second surface opposite to the first surface. The first polymer via passes through the base structure from the first surface to the second surface. The cladding layer is surrounding the first polymer via, wherein a refractive index of the cladding layer is different than a refractive index of the first polymer via. The optical coupler is disposed over the optical connector element, wherein the optical coupler receives optical signals from the first polymer via.

Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.

Abstract: A probe head includes a pair of pre-bent probes and a guide plate. The pair of probes electrically connects the electronic device integrated within a semiconductor wafer to the testing equipment. Each probe includes a tip, bottom, and body. The tip has a contact tip that contacts the corresponding contact area on the electronic device during testing. The body extends between the tip and bottom along a longitudinal development axis, and the cross-section of the body is perpendicular to the longitudinal development axis. The guide plate has a pair of guide holes configured to slidably accommodate the pair of probes. The pair of probes is arranged in a direction parallel to the cross-section, and the direction is substantially perpendicular to the buckling direction of the probes. The cross-section of each probe is substantially rectangular, and the center line of the two cross-sections passes through the short sides of each cross-section.

Abstract: A semiconductor package includes a first integrated circuit and a first waveguide. The first integrated circuit includes an optical coupler. The first waveguide is optically coupled to the optical coupler. In some embodiments, the first waveguide protrudes beyond the optical coupler. In some embodiments, the first waveguide is partially overlapped with the optical coupler.